Keywords

1 Introduction

Owing to small size and low power consumption, single-electron transistors (SETs) are becoming an attractive alternative in the post-CMOS era of semiconductor technology [1,2,3,4]. They operate on the principles of Coulomb blockade and quantum mechanical tunneling (QMT), depicting the on and the off states of the device, respectively [5,6,7]. SETs have proved their potential to be a promising candidate for non-volatile memory as well as logic applications [2, 3, 8]. SET-MOS hybridization is also one huge field of interest for logic development. It is envisaged that SETs can outperform CMOS in nanometer regime with its virtues like ultra-low power consumption and scalability [2, 3, 9]. Since last two decades, many researchers have worked to overcome two fundamental issues of SETs, viz., (a) mass production and (b) room temperature operation. In recent years, with advent in time and technology, many CMOS-compatible processes are demonstrated for fabrication of SETs [2, 4, 10,11,12]. They include nanodamascene processes [4], patterning with reactive ion etching and electromigration, chemical mechanical polishing-based fabrication [10], self-assembly and self-alignment of quantum dots [11], even optical lithography of silicon nanowire [12]. Thus, prospects of integrating SETs in a CMOS process are bright. However, room temperature operation is still a matter of experimentation.

Coulomb blockade is inherently a low energy phenomenon [6, 7]. Hence, it cannot be detected at ambient temperatures easily. So, to observe the SET operation in true sense, the device needs to be engineered carefully. The material and dimensions of island play crucial role in tunneling of electron between source and drain. Hence, the effect of island on SET drain current along with CB and QMT must be observed. The structure of island should also be compatible with the CMOS fabrication processes. In this paper, we will present the rudiments of SET design followed by a detailed analytical approach. We will then simulate the device demonstrating thorough island engineering. Results show occurrence of both, the Coulomb blockade and the quantum mechanical tunneling in the optimized device. Finally, we will present validation of our device with MIB model [3].

2 SET Design Considerations

As shown in Fig. 1, a SET consists of two tunnel junctions on source and drain sides sandwiching a quantum dot. Every junction offers a barrier—popularly known as Coulomb blockade—to flow of electrons. These junctions or barriers ensure weak coupling of source and drain with the quantum island. An electron from source, after overcoming Coulomb blockade energy level, enters the island by the process of tunneling. Simultaneously, an electron leaves the island and tunnels to the drain, causing current to flow. Thus, to ensure the charge transfer, one needs to supply Coulomb energy to the island. This energy can be supplied by an external voltage source. It is given by [5,6,7],

Fig. 1
figure 1

Structural schematic of single-electron transistor

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$${E}_{C}=\frac{{e}^{2}}{{2C}_{\sum }}$$
(1)

where C∑ is the capacitance of the island given by (2CJ + CG), CJ being the tunneling junction capacitance. Correspondingly, Coulomb voltage is given by

$$V_{\mathrm{CB}} = \frac{e}{{2C}_{\sum }}$$
(2)

This capacitance is primarily governed by the device geometry and material parameters. With reduction in this capacitance, EC increases, making the junction more opaque.

In addition to this capacitive coupling, the barrier offers tunnel resistance, which must be larger than the fundamental resistance \({R}_{T}\gg \boldsymbol{ }\frac{\boldsymbol{\hslash }}{{{\varvec{q}}}^{2}}\), that is, approximately 25.8 KΩ [5,6,7]. It ensures localization of electron states to the island during blockade. RT also controls the driving capability of the device. The device maximum operating frequency is 1/(RTC) [9]. Conflict of speed and power can be addressed by fine tuning these two electrical parameters. This demands appropriate materials choice and fabrication of capacitors of the order of attofarads, which is possible in today’s era.

For designing a rugged SET, Coulomb energy of the SET should be sufficiently higher than the ambient thermal energy. Table 1 illustrates capacitance and bias requirements with respect to thermal robustness. General trend dictates acceptable range as 20 KBT.

Table 1 Capacitance and bias requirements with respect to thermal robustness
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It is evident from Table 1 that for room temperature operation of SETs, appropriate tunnel junction engineering and optimization is crucial so as to obtain: (a) very low total capacitance (aF), (b) high driving current (nA) and (c) very low thermionic current (during opaque state of the junction). A low-k dielectric like SiO2 can offer a barrier less than 0.4 eV [13] aiding high level of transparency. But for junction opacity, high-k dielectric like TiO2 which offers barrier greater than 1 eV is required. To resolve this conflict, Hajjam et al. proposed multi-dielectric stack to control the off current [13]. However, it involved realizing ultra-thin layers of various dielectric increasing design and process complexity. We propose that instead of tunnel engineering, one can opt for island engineering to achieve acceptable ION and IOFF values. It is comparatively easy, simple to comprehend and process-friendly.

Figure 2a, b shows structure and MIB model of a single-gate SET [3]. Source, drain and gate are made up of n-polysilicon (phosphorus, 1e19 cm−3), whereas the substrate is p-silicon (boron, 1e15 cm−3). Tunneling junction capacitances on source as well as drain side are CTD = CTS = CJ, control gate capacitance is CG, tunnel junction resistances are RTD = RTS = RT = 1 MΩ. The total device capacitance is defined as CΣ = 2CJ + CG. SET design parameters compatible with BSIM predictive technology model (PTM) [14] and 22 nm node CMOS model operation at T = 300 K are chosen. Consequently, supply voltage is chosen to be 0.8 V. For a robust reliable design of SET logic, which can operate with the least possible error at room temperature, the charging energy EC must be as large as possible compared with the thermal energy. As such, Coulomb/charging energy = e2/CΣ = 40 KBT = 1.036 eV. This leads to a value of 0.155 aF for CΣ. So, Coulomb blockade voltage = e/2CΣ = 0.51 V. Control gate capacitance = e/2VDD = 0.045 aF. Hence, junction/tunnel capacitance = (CΣ – CG)/2 = 0.055 aF. Background charge is neglected.

Fig. 2
figure 2

a Single-gate SET structure, b equivalent MIB model where tunnel barriers are represented by parallel RC combinations (RTS || CTS and RTD || CTD), gate dielectric as gate capacitance CG, conductive island as black dot and two bias supplies, namely, VDS and VGS between drain––source and gatesource, respectively [3]

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3 Island Engineering

Figure 3 shows top view of single-gate SET under consideration.

Fig. 3
figure 3

Top view of single-gate SET

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Table 2 illustrates SET electrical parameters and their possible mapping with its physical parameters. Our strategy is to play with island and junction dimensions while maintaining overall device dimension constant. The tunnel barrier engineering plays a vital role for this work to choose the tunnel barrier thickness [15]. We have experimented with aluminum and copper as island material, due to general good conductivity. In TCAD simulations, for global device, we used Philips Unified Mobility Model because it incorporates doping and temperature dependencies. For modeling tunneling near insulator for rapidly varying field, we used band-to-band and Schenk recombination models [16]. At material interfaces, we also used direct tunneling model as the barrier is trapezoidal [15, 16]. Junction width less than 3 nm did not result in satisfactory Coulomb blockade and greater than 4 nm did not show tunneling in the neighborhood of bias voltage. Under no influence of gate, devices exhibit blockade and tunneling as shown in Fig. 4a, b, for aluminum and copper island, respectively.

Table 2 Physical and electrical parameters of SET
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Fig. 4
figure 4

VD–ID characteristics of single-electron devices for a aluminum island and b copper island for different island dimensions

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The devices clearly show the mechanisms of Coulomb blockade and quantum mechanical tunneling. In the limiting case of small structures, the structure resistivity becomes proportional to ρ0 * λ for any given fixed dimension [17], where ρ0 and λ are the bulk resistivity and mean free path for electron phonon scattering, respectively. Thus, the metal with the lowest product ρ0 * λ is expected to exhibit the highest conductivity. This product is 6.70e–16Ω m2 for copper and 5.01e–16Ω m2 for aluminum [17]. Hence, the current capacity of aluminum devices is higher than the copper devices. Coulomb voltage and SET capacitances extracted from above profiles for all the devices are listed in Table 3.

Table 3 Derived and extracted parameters of SET
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First observation here is that copper island devices offer better confinement than their aluminum counterparts. Small islands have higher Coulomb voltage. This is attributed to increased confinement and hence higher blockade. It is also observed that the extracted values have higher degree of matching as the device capacitance becomes smaller and smaller. Effect of island dimension and material can be seen in Fig. 5.

Fig. 5
figure 5

I–V profiles for variation in materials and dimensions of island and junction

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So, it is found that bigger island leads to higher Coulomb blockade and lower drain current.

Finally, we settled for Device A with aluminum island (CG = 0.045 aF, CJ = 0.035 aF) and simulated it for the bipolar I–V behavior. Result obtained is shown in Fig. 6.

Fig. 6
figure 6

Output characteristics of SET using TCAD

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4 Validation

Validation of our work was done by implementing SET in cadence with the help of MIB model. Parameters extracted from the TCAD simulations were used for implementing MIB model [3]. The model setup and various results are as shown in Fig. 7a–d.

Fig. 7
figure 7

a Electric field approaching at island, b simulated electric field of SET, c and d transfer and output characteristics of SET using MIB

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Clear-cut manifestation of Coulomb blockade, tunneling and Coulomb oscillations indicate successful implementation of the designed device. Effect of gate voltage can be easily seen in both output as well as the transfer characteristics.

Comparison of our technique with other groups peer work is mentioned in Table 4.

Table 4 Comparison of proposed SET with other peer work with respect to various electrical and physical parameters
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5 Conclusion

Owing to modern technological inventions, it is possible to fabricate very small capacitive structures. Hence, SET has a potential to operate at room temperature in ultra-low power applications. Island engineering can be sought as simplest method for optimizing SET. The aluminum island device simulated here gives a stable room temperature operation with a current of the order of 10 nA and is compatible with BSIM predictive technology model (PTM) and 22 nm node CMOS model. The device can operate at a bias voltage of 0.8 V and can be used in logic as well as memory applications. The proposed technique is simple and easily realizable compared with the other techniques proposed.