Abstract
This paper presents reconfigured dual-memory controller-based VLSI architecture for discrete wavelet transform to meet the wide variety of diverse computing requirements of the future generation system on chip designs. The proposed architecture mainly consists of a reconfigured DWT processor with dedicated memory which enhances the overall performance of the design. Generally any image and video processing algorithm memory plays are major criteria in determining the overall performance of the design. We have designed and implemented a dual-memory controller DWT processor on ZedBoard. This created dual-memory controlled DWT IP can be reconfigured as per designer requirement for high-end application. The DWT is applied to various images, and the compression ratio is obtained. The above architecture is implemented in SoC XC7Z020 FPGA, and the results show that architecture has reduced memory, low power consumption, and high throughput over several designs. The performance is compared with the available architectures showing good agreements. The area utilized by the DWT architecture is 13%, the delay is 11.577 ns, and the total on-chip power consumption is 23.8 mW. The number of slice LUTs and slice registers utilized for the design is 912 and 1469, respectively.
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I would thank the CoreEL Technologies Pvt Ltd for providing the various facilities and resources available. I would also thank KLE Dr. M.S.S.CET, Belagavi, for their support in completing this work.
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Naik, P., Guhilot, H., Tigadi, A., Ganesh, P. (2019). Reconfigured VLSI Architecture for Discrete Wavelet Transform. In: Wang, J., Reddy, G., Prasad, V., Reddy, V. (eds) Soft Computing and Signal Processing . Advances in Intelligent Systems and Computing, vol 898. Springer, Singapore. https://doi.org/10.1007/978-981-13-3393-4_72
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DOI: https://doi.org/10.1007/978-981-13-3393-4_72
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