Abstract
Digital signal processor (DSP) is widely used in wireless communications to compute fast Fourier transform (FFT) or its inverse (IFFT). This paper presents the butterfly unit (BU) suitable for DSP to compute FFT/IFFT. The dynamic range of input sequence is increased by representing them using 16-bit floating format. The BU performs trivial addition as well as complex multiplication in a single cycle. The proposed BU is free from multiple processing elements. This BU also eliminates the rounding of twiddle coefficients occurred in fixed-point data representation and reduces the error.
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Acknowledgements
The authors would like to thank Mr. Shirish Joshi, Director, A.D.M., Mumbai for providing software and hardware support to carry out this work. Thanks are also due to Ms Surabhi Crasto for her non-technical support.
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Kulkarni, P., Hogade, B.G., Kulkarni, V. (2019). Designing of Radix-2 Butterfly for Digital Signal Processor for FFT Computation. In: Satapathy, S., Joshi, A. (eds) Information and Communication Technology for Intelligent Systems . Smart Innovation, Systems and Technologies, vol 107. Springer, Singapore. https://doi.org/10.1007/978-981-13-1747-7_59
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DOI: https://doi.org/10.1007/978-981-13-1747-7_59
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