Keywords

3.1 Introduction

From a practical point of view of technology qualification, it is important to know the magnitude of Bias Temperature Instability (BTI) at end-of-life of devices and hence of circuits and products under normal use condition. Estimation of Negative BTI (NBTI) and Positive BTI (PBTI) respectively in p- and n-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is usually done by stressing the devices at higher than normal gate bias (V G = V G-STR) and measuring the resulting device parametric degradation with minimal impact of recovery artifacts. Different “recovery-free” measurement techniques have been discussed in Chap. 2. As mentioned before, stress tests are usually performed for few hours or days in wafer level setup, although sometimes the test can go on for few months in package level setup. Measured data at short time and at accelerated aging condition are then extrapolated to end-of-life and normal operating condition by using suitable models. Proper understanding of BTI degradation mechanism is necessary to develop reliable extrapolation models. It also helps in understanding the impact of gate insulator processes on BTI, which in turn helps in process optimization for keeping BTI under acceptable limits for technology qualification.

The physical mechanism of BTI has remained as a topic of great debate. It was discussed in Chap. 1 that NBTI has emerged as a crucial p-MOSFET reliability issue since 90 nm technology node, when Silicon Oxynitride (SiON) replaced Silicon Dioxide (SiO2) as the gate insulator [1, 2]. NBTI remains as an important issue even today for planar MOSFETs and FinFETs having state-of-the-art High-K Metal Gate (HKMG) gate stacks [3, 4]. Over the years, different physical mechanisms have been proposed to explain buildup of positive charges in the gate insulator during NBTI stress and were recently reviewed [5]. Figure 3.1 shows schematic of p- and n-channel HKMG MOSFETs having bi-layer gate insulator stack with SiO2 or SiON Interlayer (IL) and Hafnium Oxide (HfO2) High-K dielectrics. Positive charge buildup during NBTI stress can be due to either one or both of the two processes, i.e., generation of new traps at or near the interface between Silicon (Si) channel and SiO2 (or SiON) IL and/or charging of pre-existing, as-processed traps in IL bulk . It is believed that HfO2 High-K layer presumably acts primarily as a voltage divider.

Fig. 3.1
figure 1

Schematic of p- and n-channel HKMG MOSFETs showing different trap generation (TG) and trapping (TP) processes under NBTI and PBTI stress

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Different characterization techniques have been discussed in Chap. 2 for accessing the density of process related and generated traps respectively before and after BTI stress. Note that direct characterization techniques such as Charge Pumping (CP) [6] and Gated Diode (or DCIV) [7] have been used in several reports to provide irrefutable proof of interface trap generation (ΔNIT) for NBTI stress in SiON [5, 7–15] and HKMG [5, 16–18] p-MOSFETs. In spite of these experimental evidences, some reports have suggested hole trapping in pre-existing traps (ΔNHT) as the only NBTI mechanism [19–23], which is definitely not correct. Similarly, reports suggesting ΔNIT as the exclusive NBTI mechanism [10, 11] are also not correct, as they cannot explain ultra-fast threshold voltage shift (ΔV T) measurements [20, 24, 25] and gate insulator process dependence of NBTI [13–15]. As of today, the prevailing notion of NBTI mechanism involves contribution from both ΔNIT and ΔNHT; although some have suggested strong coupling or correlation between the two processes [26], most reports suggest that they are independent and mutually uncorrelated [5, 9, 13–18, 27–35]. Furthermore, trap generation (ΔNOT) in bulk IL also contributes for situations involving high stress gate bias (V G-STR). Mutually uncoupled ΔNIT and ΔNHT (and also ΔNOT for certain situations) mechanisms can explain different gate insulator process dependent NBTI data [5, 33–35], and is discussed later in Chap. 4.

As discussed in Chap. 1, PBTI remained negligible for SiON n-MOSFETs and became important with the introduction of HKMG technology [36]. As mentioned before, NBTI in HKMG MOSFETs results in positive charge buildup in the SiO2 or SiON IL due to trap generation at Si/IL interface and hole trapping in IL bulk [16, 17, 34]. In contrast, PBTI results in negative charge buildup in HfO2 High-K layer as shown in Fig. 3.1 [36]. Note that initial HKMG MOSFETs had thick and not fully optimized HfO2 High-K layer and showed very large PBTI degradation primarily due to significant electron trapping in pre-existing traps (ΔNET) [37, 38]. However, PBTI magnitude reduces with reduction in High-K layer thickness [36] and with optimization of HKMG process [39] as mentioned in Chap. 1. For well-optimized gate insulator stacks, various reports have suggested trap generation in the High-K layer measured directly using DCIV [16, 17, 40] and Stress Induced Leakage Current (SILC) [40, 41] methods. Moreover, a recent report has suggested two different and mutually uncoupled PBTI trap generation processes, presumably at the IL/High-K interface (ΔNIT-HK) and High-K bulk (ΔNOT-HK), respectively, probed by DCIV and SILC techniques [17]. In spite of such direct experimental evidences of trap generation , some report still suggests PBTI to be solely due to electron trapping in pre-existing process related traps in the High-K layer even for state-of-the-art technology nodes [42], which is obviously not correct. However, many reports have suggested mutually uncorrelated trap generation and trapping in High-K as the physical mechanism of PBTI [16, 17, 32, 40, 43]. PBTI model is discussed later in Chap. 4.

Furthermore, transconductance degradation (Δg m ) has been reported for NBTI stress in HKMG p-MOSFETs since generated IL charges are closer to the channel and results in mobility degradation due to Coulomb scattering. However, Δg m is negligible for PBTI stress in well-optimized HKMG n-MOSFETs due to negligible IL degradation [39], refer to Chap. 1 for details. While the magnitude of PBTI degradation reduces with HfO2 thickness scaling, it increases with reduction in IL thickness since generated High-K layer charges come closer to the channel, and also due to possible modification of the High-K layer quality introduced by the IL thickness scaling process [17, 32, 44, 45]. Therefore, NBTI and PBTI charges are shown to have very different physical location in the HKMG gate stack.

As mentioned in Chap. 1, the relative magnitude of NBTI and PBTI degradation respectively in p- and n-channel HKMG MOSFETs stressed under identical oxide field (E OX) and temperature (T) depends on the gate insulator process and is industry specific [3, 4]. Although NBTI results in trap generation and trapping in the IL layer while PBTI degrades the High-K layer, they demonstrate very similar behavior listed as follows, when measured by using Ultra-Fast Measure-Stress-Measure (UF-MSM) technique, refer to Chap. 1 for details:

  1. (a)

    Time evolution of ΔV T shows rapid increase at the beginning of stress and power-law time dependence with time exponent n for longer stress time . The longer time power-law dependence is observed for both DC and AC stress , refer to Figs. 1.25 and 1.30.

  2. (b)

    The longer time power-law time exponent n is independent of stress E OX and T when stress and measurements are performed without any extraneous artifacts, such as influence of recovery or stress saturation , and shows similar values for NBTI and PBTI stress. The exponent is also independent of AC pulse duty cycle (PDC) and frequency (f), although n for AC stress is higher compared to DC stress . Refer to Figs. 1.26 and 1.31.

  3. (c)

    Measured ΔV T increases with stress E OX and T. The power-law E OX acceleration factor (ΓE) and Arrhenius T activation energy (E A) extracted using ΔV T measured at fixed stress time (t STR) are found to be independent of stress T and E OX respectively, when stress and measurements remain free from certain extraneous artifacts mentioned above, refer to Fig. 1.27.

  4. (d)

    BTI recovery results in lower ΔV T for AC when compared to DC stress. AC ΔV T is independent of f, and shows a typical “S” shaped characteristic with variation in PDC , with a large “kink” or “jump” in ΔV T observed between high PDC AC and DC stress, refer to Fig. 1.32.

  5. (e)

    Although the magnitude of ΔV T increases for NBTI but reduces for PBTI when Nitrogen (N) is incorporated in the gate insulator stack, the parameters n, E A and ΓE show a reduction for both NBTI and PBTI stress, refer to Fig. 1.34.

  6. (f)

    Equivalent Oxide Thickness (EOT) scaling achieved either by reduction in IL thickness or post High-K nitridation results in higher ΔV T but reduction in parameters n, E A and ΓE, refer to Fig. 1.35.

In this chapter, the underlying trap generation and trapping subcomponents of NBTI and PBTI degradation are independently assessed respectively in p- and n-channel HKMG MOSFETs. Devices having different HKMG gate insulator processes are used. The contribution of trap generation and trapping on ΔV T measured using ultra-fast MSM method is also assessed to determine physical mechanism of BTI degradation. The concept developed in this chapter will be used in Chap. 4 to develop quantitative NBTI and PBTI models.

3.2 Description of HKMG Devices

Figure 3.2 shows the gate insulator process flow of different HKMG MOSFETs studied in this chapter. A Gate First integration scheme has been used.

Fig. 3.2
figure 2

Schematic process flow of different HKMG gate insulators studied in this chapter

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The devices have different Rapid Thermal Process (RTP) based thermal IL layers [46] but identical HfO2 High-K layer obtained using the Atomic Layer Deposition (ALD) method [47]. Different pre-clean surface treatments have been used before thermal IL growth and before ALD High-K deposition. The Si/IL pre-clean is done before the IL growth and therefore affect the IL quality, and for thinner IL, it can also affect the High-K quality. The IL/HK pre-clean is done after IL growth but before High-K deposition, and impacts the High-K layer quality. EOT scaling has been achieved (a) by using RTP based thermal IL having thickness of 5 Å (D1) and 3 Å (D2), (b) by introducing Nitrogen (N) in the gate stack after High-K deposition, using Decoupled Plasma Nitridation (DPN) [48] with proper Post Nitridation Anneal (PNA) [49] (D3) and (c) by using N based surface passivation before RTP IL growth (D4). Devices D1 through D4 have identical Si/IL and IL/HK pre-clean processes, different IL but identical High-K thickness . Devices D5 through D7 have identical IL and High-K layer thickness, however, D5 and D6 have similar Si/IL but different IL/HK pre-clean processes, while D6 and D7 have different Si/IL but similar IL/HK pre-clean processes. All thicknesses are measured using X-ray Photoelectron Spectroscopy; refer to [32] for further details.

3.3 Trap Generation During NBTI

In this section, trap generation during NBTI stress in HKMG p-MOSFETs is studied using the Gated Diode or DCIV technique [7], which has been discussed in detail in Chap. 2. In this technique, the source and drain terminals of a MOSFET are shorted together and forward biased below the junction cut-in voltage, the gate is swept from accumulation to inversion, and the current due to electron-hole recombination in traps at and near the Si channel and gate insulator interface is measured at the substrate. DCIV current (I DCIV) is proportional to the density of these traps, and therefore, increase in I DCIV after NBTI stress is a direct measure of generation of new traps. In HKMG MOSFETs, DCIV can measure trap generation at Si/IL interface , IL bulk , as well as at IL/High-K interface especially for gate stacks having thin IL layers, refer to Fig. 3.1. However, it is unlikely that DCIV would probe much deeper inside High-K bulk. Therefore, in addition to generated traps associated with NBTI, DCIV technique can also measure generated traps in the IL due to Time Dependent Dielectric Breakdown (TDDB) process as both mechanisms get triggered at identical stress conditions, refer to Chap. 1, Fig. 1.2. However, as discussed in Chaps. 2 and 4, TDDB has much larger V G acceleration factor compared to NBTI [15], and for HKMG MOSFETs, the stress V G gets divided between the IL and High-K layers. Therefore, for moderate values of stress V G, trap generation in HKMG devices measured by DCIV can be largely associated to the NBTI process.

Furthermore, DCIV is a slow measurement technique and it takes approximately few seconds to perform the V G sweep and measure I DCIV using conventional instrumentation. Note that DCIV characterization is performed in MSM mode, where measurements are performed before and during logarithmically spaced intervals of NBTI stress. Since generated traps start to reduce when NBTI stress is stopped for measurement, measured DCIV data get corrupted by recovery artifacts and therefore needs to be corrected for measurement delay , as discussed in Chap. 2. Finally, note that DCIV scans trap generation located energetically in ~0.3 eV around the Si band gap [7]. Since ΔV T gets affected by trap generation in the entire band gap, measured DCIV data must also be corrected for such band gap difference before compared to ΔV T obtained from I–V measurements. DCIV data in this and following sections are plotted after correction for measurement delay and band gap difference using the procedure discussed in Chap. 2 [17].

3.3.1 DCIV Measurements in DC Stress

Figure 3.3 plots time evolution of generated interface traps (ΔNIT) in HKMG p-MOSFETs having (a) non-nitrided (D2) and (b) N surface passivated (D4) IL for NBTI stress at different V G-STR and T. As mentioned before, ΔNIT is extracted from DCIV measurements after delay and band gap correction . Only longer time data are plotted, and ΔNIT increases with increase in V G-STR and T as expected, and the nitrided device D4 shows slightly higher degradation compared to its non-nitrided counterpart due to larger stress E OX and different IL quality. Note that E OX is calculated using (V G-STR − V T0)/EOT ; where V T0 is pre-stress V T and EOT is the SiO2 equivalent gate insulator thickness . The time evolution of ΔNIT shows power-law dependence with identical time exponent (n ~ 1/6) for both devices and for different V G-STR and T. The exponent n is extracted by linear regression of measured ΔNIT time evolution data in t STR range of 10 s to 1 Ks. Interestingly, the HKMG process dependence of time exponent n for ΔNIT is different from that for ΔV T shown earlier in Chap. 1, Figs. 1.25, 1.33 and 1.35. Note that although ΔV T shows power-law time dependence with exponent n that is independent of V G-STR and T for a particular HKMG process, its value reduces for nitrided devices unlike that shown here for ΔNIT data. Moreover, the value of n for ΔNIT is always higher than that for ΔV T when extracted in the same range of t STR as shown.

Fig. 3.3
figure 3

DCIV measured time evolution of ΔNIT for NBTI stress at different V G-STR and T in HKMG p-MOSFETs having different IL processes

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As a further proof of the universality of power-law time exponent n, time evolution of ΔNIT is measured using DCIV method in different HKMG devices shown in Fig. 3.2. Figure 3.4 plots extracted n versus (a) V G-STR and (b) T after correction for measurement delay . Note that within measurement error, a universal power-law time dependence with n ~ 1/6 is obtained for devices having different HKMG gate insulator processes and also across different V G-STR and T. Once again, while a universal exponent is obtained for time evolution of ΔNIT, this is in contrast to the exponent obtained for time evolution of ΔV T from UF-MSM technique; the latter has strong gate insulator process dependence as discussed in Chap. 1, Sect. 1.6. This universality of ΔNIT time evolution is a very significant result and underlines the robustness of physical mechanism governing interface trap generation , which will be discussed later in this book.

Fig. 3.4
figure 4

Extracted long-time power-law time exponent n for different HKMG devices as a function of a stress V G and b stress T, obtained using DCIV measurements during NBTI stress

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Figure 3.5 plots (a) stress E OX and (b) stress T dependence of ΔNIT at fixed t STR, obtained from DCIV measurements after delay and band gap corrections . Experiments have been performed at three sets of stress T, and for each T, three different values of E OX have been used. This facilitates extraction of power-law E OX acceleration factor ΓE and Arrhenius T activation energy E A of ΔNIT at different T and E OX, respectively. Since ΔNIT time evolution has power-law dependence with similar n for different stress E OX and T as shown above, extracted ΓE and E A would be independent of t STR. It is interesting to note that similar to E OX and T dependence of ΔV T shown in Chap. 1, Fig. 1.27, measured values of ΓE and E A from E OX and T dependence of ΔNIT are also independent of T and E OX, respectively. Note that mutually independent E OX and T dependencies are obtained when stress and measurement remain free from extraneous artifacts mentioned in Chap. 1, Sect. 1.3.

Fig. 3.5
figure 5

Fixed time DCIV measured ΔNIT versus a stress E OX and b stress T for NBTI stress in HKMG p-MOSFETs. E OX dependence is shown for different T and T dependence shown for different E OX. E OX dependence is plotted in a log–log scale and T dependence is plotted in a semi-log scale

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Figure 3.6 shows the impact of IL thickness on (a) power-law field acceleration factor ΓE and (b) Arrhenius T activation energy E A extracted from DCIV measured ΔNIT data after delay and band gap correction, for NBTI stress in different HKMG devices shown in Fig. 3.2. As discussed before, IL thickness scaling is achieved by using different RTP based thermal IL (D1, D2), post High-K nitridation (D3), and RTP based IL on N passivated Si substrate (D4). Both ΓE and E A reduce with EOT scaling as shown, which is similar to EOT dependence of ΓE and E A for ΔV T shown in Fig. 1.35. For a particular device, the magnitude of ΓE for ΔNIT is similar to that for ΔV T, while E A for ΔNIT is always higher compared to the corresponding value for ΔV T. This aspect is discussed later in this chapter and also in Chap. 4.

Fig. 3.6
figure 6

Power-law field acceleration factor (ΓE) and Arrhenius T activation energy (E A) of DCIV measured ΔNIT for NBTI stress, as a function of IL thickness of different HKMG stacks

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3.3.2 DCIV Measurements in AC Stress

Similar to DC stress , DCIV assessment of trap generation during AC NBTI stress is also done in MSM mode, where measurements are performed before and during logarithmically spaced interruptions of stress. Figure 3.7 plots time evolution of ΔNIT during AC stress at different (a) PDC and (b) f but identical stress E OX and T, obtained from DCIV measurements after delay and band gap corrections .

Fig. 3.7
figure 7

DCIV measured time evolution of ΔNIT for AC NBTI stress at different a PDC and b frequency; the PDC and f values used in panel a and b respectively are mentioned at the top. Measured long-time power-law time exponent n as a function of c PDC for different devices and d frequency. Fixed time measured ΔNIT versus e PDC for different V G-LOW and f frequency

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Only the long t STR data are plotted, and the corresponding DC data are also shown. Note that DC stress bias and AC stress pulses have been applied for identical t STR duration, and therefore the actual duration of AC stress , i.e., the pulse on time would depend on PDC of the applied AC pulse . ΔNIT time evolution shows power-law dependence at longer t STR for both DC and AC stress, and the exponent n extracted in t STR range of 10 s to 1 Ks is also plotted in Fig. 3.7 as a function of (c) PDC and (d) f of the gate pulse ; DC value is shown as reference (100 % PDC). Identical n (~1/6) is observed for DC and AC stress at different PDC and f. Note that identical n of ΔNIT time evolution for DC and AC stress is in contrast to that observed for time evolution of ΔV T, measured using the UF-MSM technique and shown in Chap. 1, Fig. 1.31; ΔV T shows lower n for DC compared to AC stress. Moreover when extracted in same t STR range, ΔNIT shows higher n compared to ΔV T for DC stress, however, both ΔNIT and ΔV T show identical n (~1/6) for AC stress. Once again, the universality of n ~ 1/6 for ΔNIT time evolution during DC and AC stress suggest the robustness of the underlying physical mechanism of interface trap generation and is discussed in Chap. 5.

Figure 3.7 also plots measured ΔNIT at fixed t STR for AC NBTI stress as a function of (e) PDC and (f) f, the PDC dependence is measured using AC pulses having identical pulse high but different pulse low values. AC data are normalized to the corresponding DC value at identical t STR. Note that ΔNIT magnitude increases with increase in PDC , but remains independent of the pulse low value and f. Although f independence of ΔNIT is qualitatively similar to that observed for ΔV T as shown in Chap. 1, Fig. 1.32, ΔNIT and ΔV T have very different AC to DC ratio . On the other hand, the PDC dependence of ΔNIT is both qualitatively and quantitatively different from the PDC dependence of ΔV T. Note, ΔNIT does not show the “S” shaped PDC dependence as in ΔV T, and moreover, no “kink” or “jump” is seen for ΔNIT data between high PDC AC and DC stress . Furthermore, not only ΔNIT has very different AC to DC ratio compared to ΔV T as mentioned above, unlike ΔV T, the AC to DC ratio for ΔNIT does not depend on the pulse low value. Time evolution of ΔNIT and ΔV T for AC stress will be explained later in this book.

3.4 Hole Trapping During NBTI

As discussed earlier in this chapter, although interface trap generation plays a crucial role, it alone cannot explain UF-MSM measured ΔV T during NBTI stress. As an evidence of additional contribution from the hole-trapping component, Fig. 3.8 plots time evolution of measured ΔV T and ΔV IT (=q/C OX * ΔNIT) obtained using UF-MSM and DCIV techniques, respectively. Experiments were performed on HKMG p-MOSFETs having (a) non-nitrided (D2) and (b) N surface passivated (D4) IL, refer to Fig. 3.2; C OX is gate insulator capacitance and q is electronic charge. Identical stress E OX and T have been used for both devices, and experimental DCIV data were corrected for measurement delay and band gap differences as mentioned earlier. Since ΔV IT signifies the component of ΔV T that is contributed by generated interface traps (ΔNIT), the difference between ΔV T and ΔV IT signifies contribution due to hole trapping in pre-existing traps , ΔV HT (=q/C OX * ΔNHT). Time evolution of ΔV HT is also plotted in Fig. 3.8. Only longer t STR data are shown.

Fig. 3.8
figure 8

Time evolution of UF-MSM measured ΔV T and DCIV measured ΔNIT contribution after measurement delay and band gap correction (ΔV IT), for NBTI stress in HKMG p-MOSFETs having different IL processes. Extracted difference (ΔV HT) is also shown

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Time evolution of ΔV IT has power-law dependence with exponent n ~ 1/6 as discussed above, while ΔV HT saturates at longer t STR as shown. Therefore, time evolution of ΔV T (=ΔV IT + ΔV HT) shows power-law dependence with lower n compared to that for ΔV IT. This explains the reason behind lower time exponent n observed for ΔV T compared to ΔNIT data across different V G-STR and T as mentioned before. Although the ΔV IT contribution increases slightly for the N containing device D4 compared to the non-nitrided device D2, a significantly large increase is observed for the ΔV HT component. Therefore, ΔV T magnitude increases while time exponent n reduces for the D4 device as shown. Figure 3.8 clearly indicates that the underlying ΔNIT and ΔNHT components of NBTI are uncorrelated; a relatively larger increase in ΔNHT is observed for the D4 device having N in the gate stack, which can explain the measured reduction in the time exponent n. However, ΔV IT component dominates ΔV T for both devices as shown.

As a further proof, Fig. 3.9a shows the correlation of measured ΔV T and ΔV IT for HKMG devices D2 and D4. As mentioned before, ΔV T is obtained using UF-MSM and ΔV IT using DCIV after delay and band gap correction . The 1:1 correlation line is also shown, which signifies zero hole-trapping contribution. Note that for a particular ΔV IT, D2 device shows slightly higher ΔV T than the 1:1 correlation line, while a somewhat larger ΔV T is observed for device D4, which is consistent with relatively larger ΔNHT contribution for device D4 having N in the gate insulator stack. Larger magnitude of hole trapping during NBTI stress in gate insulators containing N is a well-known result and reported by various groups [13–15, 50].

Fig. 3.9
figure 9

a Correlation of UF-MSM measured ΔV T and DCIV measured ΔV IT for NBTI stress, and b pre-stress trap density measured by using flicker noise method, in HKMG p-MOSFETs having different HKMG gate insulator processes

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Hole trapping occurs in pre-existing, process related gate insulator traps, and as mentioned in Chap. 2, flicker noise technique can be used to access the density of these traps. In flicker noise method, the gate of the MOSFET is biased in weak inversion and the power spectral density of drain current noise (S ID) is measured using a spectrum analyzer . The inversion layer carrier density in the channel remains low in weak inversion, and drain current noise arises due to trapping and detrapping of carriers in gate insulator traps. Higher trap density results in larger S ID and vice versa. Figure 3.9b shows measured pre-existing trap density in devices D2 and D4. Note that the nitrided device D4 shows higher trap density, which is consistent with higher ΔNHT contribution shown in Figs. 3.8 and 3.9a. The impact of N on pre-existing hole traps has been studied in detail in SiON [50] and HKMG [51] p-MOSFETs and also verified by Density Functional Theory (DFT) calculations as discussed in detail in [17, 51].

Time evolution of ΔV T and ΔNIT during NBTI stress has been measured respectively using UF-MSM and DCIV methods for three sets of stress T, and for each T, three different E OX values have been used for stress. The E OX and T dependencies of ΔV T at fixed t STR are shown in Chap. 1, Fig. 1.27 and that for ΔNIT are shown before in Fig. 3.5. Measured ΔV T and ΔV IT as well as the extracted difference ΔV HT obtained at a fixed t STR for the HKMG device D4 are plotted in Fig. 3.10a versus stress E OX for a particular stress T, and plotted in Fig. 3.11a versus stress T for a particular stress E OX. Note that the ΔV IT subcomponent dominates overall ΔV T for all E OX and T, even for D4 device having N in the gate insulator stack. Moreover, identical power-law E OX dependence ΓE is obtained for ΔV T, ΔV IT and therefore for ΔV HT. However, extracted ΔV HT has much lower Arrhenius T activation energy E A compared to measured ΔV IT, which explains lower E A for ΔV T when compared to E A for ΔV IT as shown.

Fig. 3.10
figure 10

a Fixed time UF-MSM measured ΔV T, DCIV measured ΔV IT and their difference (ΔV HT) versus NBTI stress E OX plotted in a log–log scale. b Extracted power-law field acceleration factor for ΔV T, ΔV IT and ΔV HT versus stress T

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Fig. 3.11
figure 11

a Fixed time UF-MSM measured ΔV T, DCIV measured ΔV IT and their difference (ΔV HT) versus NBTI stress T plotted in a semi-log scale. b Extracted T activation energy for ΔV T, ΔV IT and ΔV HT versus stress E OX

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As discussed before, ΔV T and ΔN IT have power-law time dependence with identical n across different E OX and T, although n for ΔN IT is higher than that for ΔV T. Therefore, extracted ΓE and E A for ΔV T, ΔV IT and hence for ΔV HT would be independent of the value of t STR used for extracting E OX and T dependence, otherwise these terms would not have much meaning. Extracted ΓE versus T for ΔV T and its ΔV IT and ΔV HT subcomponents is shown in Fig. 3.10b, while the corresponding E A versus E OX relation is shown in Fig. 3.11b. Note that in the absence of different extraneous artifacts mentioned in Chap. 1, Sect. 1.3, ΓE and E A for both ΔV T and ΔNIT (or ΔV IT) are independent of T and E OX respectively as shown. Therefore, ΓE and E A of extracted ΔNHT (or ΔV HT) also has the same behavior as shown. Mutually uncoupled ΓE and E A is observed for other devices, not plotted here for brevity.

3.5 Trap Generation During PBTI

In this section, trap generation during PBTI stress in HKMG n-MOSFETs is studied using the DCIV [7] and SILC [41] techniques. DCIV scans trap generation located energetically in ~0.3 eV around the Si band gap, and in HKMG MOSFETs, it can measure generated traps at Si/IL interface , IL bulk , as well as at IL/High-K interface especially for gate stacks having thin IL layers. As mentioned before, negligible g m degradation during PBTI stress suggests negligible IL degradation and therefore, PBTI is believed to cause trap generation and trapping predominately in the HfO2 High-K layer [36, 39]. DCIV measurements can probe trap generation during PBTI stress at and near the IL/High-K interface (ΔNIT-HK); refer to Fig. 1. As mentioned before, it is unlikely that DCIV method would probe much deeper into the High-K bulk .

As discussed in Chap. 2, SILC is estimated from measured gate current (I G) before and during logarithmically spaced intervals of BTI stress. Increase in I G after stress is due to trap assisted tunneling via newly generated traps, and therefore, the magnitude of increased gate current (ΔI G) can be used to estimate density of generated traps during PBTI stress in HKMG n-MOSFETs [40]. Note that SILC has been used in the past to estimate gate insulator trap generation associated with the TDDB process [52–54], and also bulk trap generation during NBTI stress [55], in SiON MOSFETs. SILC is negligible during NBTI stress in HKMG p-MOSFETs due to band alignment issues mentioned in Chap. 2, while non-negligible SILC is observed in HKMG n-MOSFETs during PBTI stress [3, 16, 17, 40, 41]. Note that unlike DCIV that scans traps that are energetically aligned with Si mid gap, SILC scans traps close to the conduction band edge of the High-K layer [41]. However, there is a debate regarding the exact physical location of generated traps during PBTI stress in HKMG n-MOSFETs as probed by SILC; some report suggests it is at the IL/High-K interface [56], while other suggests it is deeper inside the High-K bulk [41]. Although the exact location of traps is an important aspect especially from the viewpoint of TDDB process, the type of generated traps probed by SILC has been found to have much smaller impact on PBTI degradation when compared to the impact of generated traps probed by the DCIV method [17], and will be discussed later in Chap. 4.

3.5.1 DCIV Measurements in DC Stress

Figure 3.12 plots the time evolution of generated interface traps (ΔNIT-HK) during PBTI stress at different V G-STR and stress T in HKMG n-MOSFETs with (a) non-nitrided (D2) and (b) N surface passivated (D4) IL. As mentioned before, ΔNIT-HK is extracted from DCIV measurements after delay and band gap correction. The delay correction of DCIV is straightforward and the method used for NBTI can be used. However, the band gap correction is not obvious, as DCIV probes traps at or near the IL/High-K interface for PBTI stress, and the exact energetic extent of trap generation is yet unknown. For simplicity, a similar correction factor as used for NBTI stress is also assumed for PBTI stress in different HKMG devices.

Fig. 3.12
figure 12

DCIV measured time evolution of ΔNIT-HK for PBTI stress at different V G-STR and T in HKMG n-MOSFETs having different IL processes

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Only longer time data are plotted, and measured ΔNIT-HK increases with increase in V G-STR and T as expected. However unlike NBTI, the ΔNIT-HK magnitude reduces significantly for the nitrided device D4 when compared to the non-nitrided device D2 at identical V G-STR and T. This happens in spite of higher E OX for device D4 due to lower EOT , E OX being calculated as (V G-STR − V T0)/EOT, and hence is attributed to presence of N in the gate insulator stack. Similar to NBTI, time evolution of ΔNIT-HK for PBTI stress shows power-law dependence with identical time exponent (n ~ 1/6) for both devices and for different V G-STR and T; the exponent n is extracted by linear regression of measured ΔN IT-HK time evolution in t STR range of 10 s to 1 Ks. Remarkably, identical n has been obtained for both NBTI and PBTI stress as shown. Note that similar to NBTI stress data shown earlier, the process dependence of ΔNIT-HK time exponent for PBTI stress is in contrast with process dependence of ΔV T time exponent shown in Chap. 1, Figs. 1.25 and 1.33. Although ΔV T has power-law dependence for PBTI stress with time exponent n that is independent of stress E OX and T for a particular HKMG process, the value of n reduces for nitrided devices, unlike that seen here for ΔNIT-HK data. Moreover, similar to that observed for NBTI stress, the value of n for ΔNIT-HK is always higher than n for ΔV T for PBTI stress, when extracted in the same range of t STR as shown.

As a further proof of the universality of time exponent (n ~ 1/6) for PBTI stress, time evolution of ΔN IT-HK is measured by using DCIV in different HKMG devices listed in Figs. 3.2, and 3.13 plots extracted n as a function of (a) V G-STR and (b) T after correction for measurement delay . Similar to NBTI, power-law time dependence with universal n ~ 1/6 is also obtained for ΔNIT-HK during PBTI stress at different V G-STR and T in devices having different HKMG gate insulator processes. Once again, similar to NBTI results shown earlier, while a universal n ~ 1/6 exponent is obtained for time evolution of ΔNIT-HK for PBTI stress in different HKMG devices, this is in contrast to the exponent obtained for time evolution of ΔV T from UF-MSM technique; the latter shows strong gate insulator process dependence as discussed in Chap. 1, Sect. 1.6. The similarity of time evolution of ΔNIT for NBTI and ΔNIT-HK for PBTI stress is a very remarkable result and underlines the similarity of physical mechanism governing trap generation at Si/IL and IL/High-K interfaces, and will be discussed later in this book.

Fig. 3.13
figure 13

Extracted long-time power-law time exponent n for different HKMG devices as a function of a stress V G and b stress T, obtained using DCIV measurements during PBTI stress

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Similar to NBTI results shown earlier, ΔNIT-HK time evolution for PBTI stress also has power-law dependence with similar n across different stress E OX and T as shown. Therefore, the power-law E OX acceleration factor ΓE and Arrhenius T activation energy E A for ΔNIT-HK extracted at a fixed t STR would remain independent of t STR. PBTI experiments were done at three sets of stress T, and at each T, three different E OX values have been used for stress. Figure 3.14 plots (a) stress E OX and (b) stress T dependence of ΔNIT-HK obtained from DCIV measurements after delay and band gap corrections . Measured values of ΓE and E A extracted from E OX and T dependence of ΔNIT-HK for PBTI stress are independent of T and E OX, respectively. This behavior is similar to the E OX and T dependent parameters of ΔV T shown in Chap. 1, Fig. 1.27. Moreover, this observation is identical to the NBTI results discussed before in this chapter. As mentioned before, mutually independent E OX and T dependencies are observed when stress and measurements remain free from artifacts mentioned earlier in Chap. 1, Sect. 1.3.

Fig. 3.14
figure 14

Fixed time DCIV measured ΔNIT-HK versus a stress E OX and b stress T for PBTI stress in HKMG n-MOSFETs. E OX dependence is shown for different T and T dependence shown for different E OX. E OX dependence is plotted in a log–log scale and T dependence is plotted in a semi-log scale

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Figure 3.15 plots the impact of IL thickness on (a) power-law field acceleration factor ΓE and (b) Arrhenius T activation energy E A extracted from DCIV measured ΔNIT-HK data after delay and band gap corrections, obtained for PBTI stress in different HKMG devices shown in Fig. 3.2. Reduction in IL thickness is achieved using different RTP based thermal IL (D1, D2), post High-K nitridation (D3), and RTP based IL on N passivated Si substrate (D4), refer to Fig. 3.2. Similar to NBTI, ΓE for PBTI reduces with EOT scaling. However unlike NBTI, only negligible reduction in E A has been observed with EOT scaling . Similar to NBTI results shown before, the magnitude of ΓE for ΔNIT-HK is similar to ΓE for ΔV T for a particular device also for PBTI stress, while E A for ΔNIT-HK is always higher compared to the corresponding value for ΔV T; refer to Chap. 1, Fig. 1.35 for dependence of ΔV T parameters on IL thickness. This aspect will be discussed later in this chapter.

Fig. 3.15
figure 15

Power-law field acceleration factor (ΓE) and Arrhenius T activation energy (E A) of DCIV measured ΔNIT-HK for PBTI stress, as a function of IL thickness of different HKMG stacks

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3.5.2 DCIV Measurements in AC Stress

DCIV assessment of trap generation during AC stress is done in MSM mode similar to DC stress , and measurements were performed before and during logarithmically spaced stress intervals. Figure 3.16 plots time evolution of ΔNIT-HK during AC stress at different (a) PDC and (b) f but identical stress E OX and T, obtained from DCIV measurements after delay and band gap corrections . Only long t STR data are plotted, and the corresponding DC data are also shown. Similar to NBTI stress as discussed before, the DC stress bias and AC stress pulses for PBTI stress were applied for identical t STR duration, and actual duration of AC stress depends on PDC of the applied AC pulse . Time evolution of ΔNIT-HK shows power-law dependence at longer t STR; the exponent n extracted in t STR range of 10 s to 1 Ks is also plotted in Fig. 3.16 as a function of (c) PDC and (d) f of the gate pulse. The DC value is shown as reference.

Fig. 3.16
figure 16

DCIV measured time evolution of ΔNIT-HK for AC PBTI stress at different a PDC and b frequency; the PDC and f values used in panel a and b respectively are mentioned at the top. Measured long-time power-law time exponent n as a function of c PDC for different devices and d frequency. Fixed time measured ΔNIT-HK versus e PDC for different V G-LOW and f frequency

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Similar to NBTI stress results shown earlier, identical n (~1/6) is observed for DC and AC PBTI stress at different PDC and f. Once again, similar to NBTI , identical n of ΔNIT-HK time evolution for DC and AC PBTI stress is in contrast to the observed time evolution of ΔV T measured using UF-MSM technique and shown in Chap. 1, Fig. 1.31; ΔV T time evolution has lower n for DC compared to AC stress . Moreover when extracted in the same t STR range, ΔNIT-HK shows higher n compared to ΔV T for DC stress , but both ΔNIT-HK and ΔV T show identical n (~1/6) for AC stress also for PBTI stress, which is again similar to NBTI stress results shown before. Once again, the universality of n ~ 1/6 for ΔNIT-HK time evolution during DC and AC PBTI stress suggest the robustness of the underlying physical mechanism of interface trap generation and will be discussed later in the book.

Figure 3.16 also plots the measured ΔNIT-HK at fixed t STR for AC PBTI stress as a function of (e) PDC and (f) f of the gate pulse . Once again, AC pulses having identical pulse high but different pulse low values were used to study the PDC dependence. AC data are normalized to the corresponding DC value at identical t STR. Similar to that shown earlier for NBTI, the magnitude of ΔNIT-HK for PBTI stress increases with increase in PDC but remains independent of the pulse low value and f of the gate pulse. Remarkably similar AC to DC ratio and PDC dependent shape has been observed for NBTI and PBTI stress. Moreover, although the f independence of ΔNIT-HK for PBTI stress is qualitatively similar to that observed for ΔV T shown in Chap. 1, Fig. 1.32, ΔNIT-HK and ΔV T show very different AC to DC ratio. This observation is similar to that reported for NBTI stress. Once again, similar to NBTI, the PDC dependence of ΔNIT-HK for PBTI stress is both qualitatively and quantitatively different from the PDC dependence of ΔV T shown in Chap. 1. Similar to NBTI results, ΔNIT-HK for PBTI also does not have the “S” shaped PDC dependence as observed for ΔV T, and unlike ΔV T, no “kink” or “jump” is observed for ΔNIT-HK data between high PDC AC and DC stress . Moreover as mentioned earlier, ΔNIT-HK has very different AC to DC ratio compared to ΔV T, and unlike ΔV T, the AC to DC ratio for ΔNIT-HK does not depend on the pulse low value. The PDC and f dependencies of ΔNIT-HK and ΔV T for AC PBTI stress have been found to be remarkably similar to AC NBTI stress as shown earlier in this chapter and also in Chap. 1.

3.5.3 SILC Measurements in DC Stress

As mentioned before, increase in gate leakage current (I G) after stress is also used to calculate trap generation during PBTI stress [40, 41]. While DCIV scans generated traps aligned energetically with the Si [7] mid gap, SILC scans traps closer to the conduction band edge of High-K layer, although the exact physical location of these traps are debated [41, 56]. I G versus V G sweeps were taken before and during logarithmic intervals of stress, and generated trap density (ΔNOT-HK) is calculated as discussed in Chap. 2 [40].

Figure 3.17 plots the time evolution of ΔNOT-HK calculated from SILC for different V G-STR and T in (a) D2 and (b) D4 HKMG n-MOSFETs; refer to Fig. 3.2 for device details. Note that SILC in HKMG devices recovers after removal of stress, and therefore, measured data must be corrected for measurement delay following the methodology shown in Chap. 2. Only long t STR data are plotted; magnitude of ΔNOT-HK increases with V G-STR and T as expected, but reduces drastically for the device D4 having N in the gate stack. Note that D4 device have thinner EOT and would have higher E OX compared to device D2 for a given V G-STR. Therefore, the reduction can be attributed to the presence of N in the gate insulator stack. It is interesting to remark that both DCIV and SILC measurements show reduced trap generation in nitrided devices during PBTI stress. Although the time evolution of ΔNOT-HK from SILC shows power-law dependence, the time exponent n is much larger when compared to that for DCIV measured ΔNIT-HK and UF-MSM measured ΔV T time evolution data shown earlier in the book.

Fig. 3.17
figure 17

SILC measured time evolution of ΔNOT-HK for PBTI stress at different V G-STR and T in HKMG n-MOSFETs having different IL processes

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As a further proof, Fig. 3.18 plots extracted time exponent n from ΔNOT-HK time evolution measured using SILC after delay correction , versus (a) V G-STR and (b) T. As done earlier, the exponent n is extracted by linear regression of measured time evolution of ΔNOT-HK data in t STR range of 10 s to 1 Ks. Data from different HKMG devices shown in Fig. 3.2 are plotted, and the trend line corresponding to DCIV data is also shown as a reference.

Fig. 3.18
figure 18

Extracted long-time power-law time exponent n for different HKMG devices as a function of a stress V G and b stress T using SILC measurements during PBTI stress. The reference line for DCIV measurement is also shown

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Note that SILC data show similar n (~1/3) for different V G-STR and T and for different devices, which signifies the robustness of the underlying physical mechanism. However, the magnitude of time exponent n from SILC is considerably higher than n (~1/6) obtained from DCIV, which unequivocally suggests different physical mechanism of generated traps that are probed by these methods. On the other hand, a remarkable similarity of extracted n has been observed during NBTI and PBTI stress for DCIV measurements, refer to Figs. 3.4 and 3.13, which suggests similar generation mechanism for these traps. This will be discussed later in this book.

Figure 3.19 plots measured ΔNOT-HK at fixed t STR from delay corrected SILC data versus (a) stress E OX and (b) stress T, for D2 and D4 HKMG n-MOSFETs. The magnitude of ΔNOT-HK reduces for the nitrided device D4, although the power-law E OX acceleration factor ΓE and Arrhenius T activation energy E A remain independent of HKMG processes. As ΔNOT-HK shows power-law time dependence and identical n across stress E OX and T, extracted ΓE and E A would be independent of t STR. Note that ΓE and E A for ΔNOT-HK obtained from SILC has much larger value when compared to ΔNIT-HK from DCIV and ΔV T from UF-MSM measurements shown earlier in the book. Different ΓE and E A also suggest different physical mechanism of generated traps as probed by DCIV and SILC techniques during PBTI stress.

Fig. 3.19
figure 19

Fixed time SILC measured ΔNOT-HK versus a stress E OX and b stress T for PBTI stress in HKMG n-MOSFETs. E OX dependence is plotted in a log–log scale and T dependence is plotted in a semi-log scale

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To understand the relative importance of different trap generation processes on PBTI degradation, Fig. 3.20 compares extracted (a) n, (b) ΓE and (c) E A for DCIV, SILC and UF-MSM measurements, as a function of IL thickness for D1 through D4 HKMG devices shown in Fig. 3.2. Note that ΔNOT-HK parameters obtained from SILC measurements remain almost constant across IL thickness and show significantly higher values when compared to the ΔV T and ΔNIT-HK parameters obtained respectively from UF-MSM and DCIV measurements. Between DCIV and UF-MSM measurements, power-law time exponent n is somewhat higher for ΔNIT-HK compared to ΔV T for all devices and n reduces with IL scaling for both ΔV T and ΔNIT-HK; however, much larger reduction is observed for ΔV T for deeply scaled IL. The power-law E OX acceleration ΓE shows similar values for ΔV T and ΔNIT-HK and reduces slightly with IL scaling. Arrhenius T activation energy E A for ΔNOT-HK remains almost constant with IL, but that for ΔV T and ΔNIT-HK reduces slightly with IL scaling. It will be shown in Chap. 4 that the voltage shift corresponding to generated bulk traps from SILC is negligible compared to that for generated interface traps from DCIV , and it is the later that dominates PBTI degradation. Therefore, the parameters n, ΓE and E A for ΔV T are closer to the parameters for ΔNIT-HK rather than that for ΔNOT-HK. Of course, additional contribution from electron trapping in High-K bulk must be considered to compute ΔV T, as discussed in the following section.

Fig. 3.20
figure 20

a Power-law time dependence n, b power-law field acceleration factor ΓE and c Arrhenius T activation energy E A obtained using UF-MSM, DCIV and SILC methods for PBTI stress, versus IL thickness of different HKMG stacks

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3.6 Electron Trapping During PBTI

Although trap generation in the IL is negligible for PBTI stress and the generated traps at or near the IL/High-K interface (ΔNIT-HK) plays a crucial role, it alone cannot explain ΔV T measured using UF-MSM method. As an evidence of additional contribution from electron trapping in pre-existing, process related High-K bulk traps (ΔNET), Fig. 3.21 plots time evolution of ΔV T and ΔV IT-HK (=q/C OX * ΔNIT-HK) respectively measured using UF-MSM and DCIV techniques. Experiments were performed in HKMG n-MOSFETs having (a) non-nitrided (D2) and (b) N surface passivated (D4) IL, refer to Fig. 3.2; C OX is gate insulator capacitance and q is the electronic charge. Identical V G-STR and T have been used for both devices, and experimental DCIV data were corrected for measurement delay and band gap differences as discussed before. Since ΔV IT-HK signifies the component of ΔV T contributed by generated interface traps at IL/High-K interface, the difference between ΔV T and ΔV IT-HK signifies the contribution due to electron trapping in pre-existing traps, ΔV ET (=q/C OX * ΔNET). Time evolution of ΔV ET is also plotted in Fig. 3.21. Only longer t STR data are plotted, and contribution from ΔV IT-HK dominates ΔV T for both devices as shown.

Fig. 3.21
figure 21

Time evolution of UF-MSM measured ΔV T and DCIV measured ΔNIT-HK contribution after measurement delay and band gap correction (ΔV IT-HK), for PBTI stress in HKMG n-MOSFETs having different IL processes. Extracted difference (ΔV ET) is also shown

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Similar to NBTI data, time evolution of ΔV IT-HK for PBTI stress shows power-law dependence with exponent n ~ 1/6 and ΔV ET saturates at longer t STR. Therefore, time evolution of ΔV T (=ΔV IT-HK + ΔV ET) shows power-law dependence with lower n compared to that for ΔV IT-HK. However contrary to NBTI, the ΔV IT-HK component of ΔV T reduces drastically for the N containing device D4 compared to the non-nitrided device D2, while an increase is observed for the ΔV ET component. Note that device D4 has lower EOT and therefore higher E OX when compared to device D2 at identical V G-STR. As ΔV IT-HK dominates overall ΔV T for both D2 and D4 devices, the magnitude of ΔV T and its power-law time exponent n reduce for device D4 as shown. Therefore, Fig. 3.21 clearly shows that underlying ΔNIT-HK and ΔNET components of PBTI are clearly uncorrelated ; i.e., while ΔNIT-HK reduces, ΔNET increases for the D4 device, which can explain the measured reduction in ΔV T and n. This aspect is further discussed in detail in Chap. 4.

As an additional proof, Fig. 3.22a plots the correlation of measured ΔV T and ΔV IT-HK for HKMG devices D2 and D4. As mentioned before, ΔV T is obtained using UF-MSM method and ΔV IT-HK using DCIV method after delay and band gap corrections . The 1:1 correlation line corresponding to zero electron trapping contribution is also plotted. Note that for a particular ΔV IT-HK, D2 device shows slightly higher ΔV T than the 1:1 correlation line. However, much larger ΔV T is observed for device D4, which is consistent with relatively larger ΔNET contribution for device D4 having N in the gate insulator stack. Larger magnitude of electron trapping during NBTI stress in gate insulators containing N has been analyzed using DFT simulations; refer to [17] for additional details.

Fig. 3.22
figure 22

a Correlation of UF-MSM measured ΔV T and DCIV measured ΔV IT-HK for PBTI stress, and b pre-stress trap density measured by using flicker noise method, in HKMG n-MOSFETs having different HKMG gate insulator processes

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Similar to hole trapping in NBTI, electron trapping during PBTI also occurs in pre-existing, process related gate insulator traps; while the hole traps are located in IL, electron traps are located in the High-K layer. As done in p-MOSFETs, flicker noise method can also be used to access the density of High-K electron traps in n-MOSFETs. Figure 3.22b shows measured pre-existing trap density in devices D2 and D4. Note that the nitrided device D4 shows higher trap density, which is consistent with higher ΔNET contribution shown in Figs. 3.21 and 3.22a, and is also consistent with DFT simulation results [17].

Similar to NBTI stress, time evolution of ΔV T and ΔNIT-HK during PBTI stress has been measured respectively using UF-MSM and DCIV methods for three sets of stress T, and for each T, three different stress E OX have been used. The E OX and T dependencies of ΔV T at fixed t STR are shown in Chap. 1, Fig. 1.27, and the same for ΔNIT are shown earlier in Fig. 3.13. Measured ΔV T, ΔV IT-HK and their difference ΔV ET at a particular t STR for the HKMG device D4 is plotted versus stress E OX at a particular stress T in Fig. 3.23a, and also plotted versus stress T for a fixed stress E OX in Fig. 3.24a. Note that ΔV IT-HK subcomponent dominates overall ΔV T for all E OX and T, even for this particular device having N in the gate insulator stack. Moreover, identical power-law E OX dependence ΓE is obtained for ΔV T, ΔV IT-HK and therefore for ΔV ET. However, ΔV ET shows much lower Arrhenius T activation energy E A compared to ΔV T and ΔV IT-HK. Note that the relative values of ΓE and E A for ΔV T, ΔV IT-HK and ΔV ET for PBTI stress are similar to that observed for NBTI stress data shown earlier in this chapter.

Fig. 3.23
figure 23

a Fixed time UF-MSM measured ΔV T, DCIV measured ΔV IT-HK and their difference (ΔV ET) versus PBTI stress E OX plotted in a log–log scale. b Extracted power-law field acceleration factor for ΔV T, ΔV IT and ΔV ET as a function of stress T

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Fig. 3.24
figure 24

a Fixed time UF-MSM measured ΔV T, DCIV measured ΔV IT-HK and their difference (ΔV ET) versus PBTI stress T plotted in a semi-log scale. b Extracted T activation energy for ΔV T, ΔV IT and ΔV ET as a function of stress E OX

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As shown before, ΔV T and ΔNIT-HK have power-law time dependence with identical n across different E OX and T, although higher n has been observed for ΔNIT-HK compared to ΔV T data. Therefore, extracted ΓE and E A for ΔV T, ΔV IT-HK and therefore for ΔV ET would be independent of the value of t STR used for extracting E OX and T dependence. Extracted ΓE for ΔV T and underlying ΔV IT-HK and ΔV ET subcomponents are plotted versus T in Fig. 3.23b, while their corresponding E A values are plotted versus E OX in Fig. 3.24b. Note that in the absence of different extraneous artifacts mentioned in Chap. 1, Sect. 1.3, ΓE and E A for ΔV T and ΔNIT-HK (or ΔV IT-HK) are shown to be independent of T and E OX, respectively. Therefore, ΓE and E A of extracted ΔNET (or ΔV ET) also show the same behavior as shown. These features of PBTI stress are exactly identical to NBTI, and similar mutually uncoupled ΓE and E A has been observed for other devices, not plotted here for brevity.

3.7 Location of Generated Traps (DCIV Measurements)

As discussed earlier in this chapter, although hole and electron trapping cannot be ignored respectively for NBTI and PBTI stress, trap generation plays the dominant role. DCIV technique has been used to access trap generation during BTI stress, and the resulting data show very similar time, bias and temperature dependence for NBTI and PBTI stress in different HKMG devices. This suggests very similar underlying physical mechanism of DCIV accessed trap generation for NBTI and PBTI. SILC is not observed for NBTI due to band alignment issues but is present for PBTI stress; although the magnitude of generated bulk traps that are responsible for SILC has been found to be smaller compared to that probed by DCIV, refer to Chap. 4 for details. DCIV accessed trap generation during NBTI and PBTI has been attributed to Si/IL and IL/High-K interfaces respectively by noting the presence or absence of degradation in g m . Trap generation in the IL in any significant quantity is ruled out for PBTI stress due to the absence of Δg m , while the presence of Δg m suggests trap generation in IL for NBTI stress. The similarities of DCIV measured trap generation during NBTI and PBTI stress have been shown before, which suggests similarity of underlying physical mechanism. In this section, experimental proof is provided to bring out their differences, which will ascertain the difference in physical location. All DCIV data shown in this section are corrected for delay and band gap using the procedure described in Chap. 2.

Figure 3.25 plots the E OX dependence of generated traps obtained at fixed t STR for (a) NBTI and (b) PBTI stress in HKMG devices having relatively thicker (D1) and thinner (D2) IL, refer to Fig. 3.2. IL thickness has no impact for NBTI stress since generated traps are at the Si/IL interface . However, magnitude of generated traps increases for thinner IL device for PBTI stress. As discussed in Chap. 5, trap generation for NBTI stress in p-MOSFETs is caused due to tunneling of inversion layer holes into the Si–H bonds at Si/IL interface, and therefore, the magnitude is independent of IL thickness. However, trap generation at or near the IL/High-K interface for PBTI stress in n-MOSFETs occurs due to tunneling of inversion layer electrons , which increases with reduction in IL thickness, and therefore causes higher trap generation magnitude for thinner IL devices as shown.

Fig. 3.25
figure 25

DCIV measured trap generation versus E OX for a NBTI and b PBTI stress in HKMG MOSFETs having different IL thickness

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Figure 3.26 plots the E OX dependence of generated traps obtained at fixed t STR for (a) NBTI and (b) PBTI stress in HKMG devices without (D2) and with (D3) post High-K nitridation using the DPN process, refer to Fig. 3.2. Nitridation impact is negligible for NBTI stress, but trap generation reduces significantly for device D3 for PBTI stress. Since N incorporation is done after High-K deposition, higher N density is expected in the High-K compared to the IL layer, especially for denser thermal IL used in this study that show much lower N penetration, refer to [51] for additional evidence from Angle Resolved X-ray Photoelectron Spectroscopy measurements. Therefore, post High-K nitridation has larger impact on generated traps at or near the IL/High-K interface for PBTI stress compared to that at Si/IL interface for NBTI stress. The exact physical mechanism responsible for reduction in trap generation for nitrided gate stacks is not known and need further study.

Fig. 3.26
figure 26

DCIV measured trap generation versus E OX for a NBTI and b PBTI stress in HKMG MOSFETs without and with nitridation after High-K deposition

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Figure 3.27 plots the EOX dependence of generated traps obtained at fixed t STR for (a) NBTI and (b) PBTI stress in HKMG devices D5 through D7 having different pre-cleans before IL growth and High-K deposition, refer to Fig. 3.2. Devices D5 and D6 have similar pre-clean before IL but different pre-clean before High-K and hence similar IL but different High-K quality. On the other hand, devices D6 and D7 have different pre-clean before IL but similar pre-clean before High-K and hence different IL but similar High-K quality. Therefore, trap generation at Si/IL interface for NBTI stress in p-MOSFETs is similar for D5 and D6 but different for D6 and D7 devices, while trap generation at or near the IL/High-K interface for PBTI stress in n-MOSFETs is different for D5 and D6 and similar for D6 and D7 devices as shown.

Fig. 3.27
figure 27

DCIV measured trap generation versus E OX for a NBTI and b PBTI stress in HKMG MOSFETs having different pre-clean processes before IL growth and High-K deposition. Refer to Fig. 3.2 for details

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Although DCIV assessed generated traps for NBTI and PBTI have similar time dynamics and EOX and T dependence, they have very different HKMG process dependence as shown in Figs. 3.25, 3.26 and 3.27 that clearly verifies the difference in physical location of these generated traps. As a further evidence, Fig. 3.28 correlates g m degradation to generated trap density measured using DCIV for NBTI and PBTI stress. Note that NBTI shows higher Δg m for a particular trap density when compared to PBTI stress. Since Δg m is due to mobility degradation resulting from Coulomb scattering by BTI charges and as trap generation dominates both NBTI and PBTI degradation, higher Δg m is caused by trap generation at Si/IL interface for NBTI than that at IL/High-K interface for PBTI.

Fig. 3.28
figure 28

Correlation of peak transconductance degradation to DCIV measured generation of traps for NBTI and PBTI stress

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Therefore, although DCIV measured traps during NBTI and PBTI stress respectively in p- and n-channel HKMG MOSFETs show very similar kinetics, they have very different physical location as discussed above.

3.8 Summary

To summarize, the underlying subcomponents of NBTI and PBTI degradation in p- and n-channel HKMG MOSFETs respectively have been analyzed using different direct characterization techniques. MOSFETs having different HKMG gate insulator processes have been studied. Process related pre-existing hole and electron traps respectively in the IL and High-K layers is accessed using flicker noise. The generation of traps during NBTI is studied using DCIV method, while that during PBTI stress using DCIV and SILC methods. The relative contribution of trapping and trap generation on BTI degradation has been accessed. Although hole trapping in IL for NBTI and electron trapping in High-K for PBTI contribute, it is observed that trap generation dominates NBTI and PBTI degradation for different HKMG gate insulator processes.

DCIV measures trap generation at Si/IL interface during NBTI and at or near IL/High-K interface during PBTI, refer to Fig. 3.1. Energetically, these traps are aligned to ~0.3 eV around the Si band gap as shown in Chap. 2. Although locations of DCIV accessed generated traps are different, at Si/IL interface for NBTI and at or near IL/High-K interface for PBTI, they show very similar time, bias, temperature, AC duty cycle , and frequency dependence between NBTI and PBTI stress, suggesting strong universality of the underlying physical process. SILC measures trap generation energetically located closer to the HfO2 conduction band, however, the exact physical location of these traps are still debated. Nevertheless for PBTI stress, SILC accessed generated traps show very different time, temperature, and bias dependence compared to that measured by DCIV and suggests very different underlying physical mechanism. SILC accessed traps have been found to have negligible role in PBTI degradation.

The following observations can be made between trap generation measured using DCIV, hole or electron trapping, and UF-MSM measured threshold voltage degradation for both NBTI and PBTI stress:

  1. (a)

    Contribution from generated interface traps, ΔV IT for NBTI or ΔV IT-HK for PBTI, shows power-law time dependence at long stress time and universal exponent n ~ 1/6 for DC stress at different E OX and T, for AC stress at different f and PDC, and for different HKMG processes. Since the trapping component, ΔV HT for NBTI or ΔV ET for PBTI, saturates at long time (n ~ 0), the relative magnitude of trap generation and trapping determines the time exponent (n < 1/6) of overall ΔV T. Trap generation and trapping are completely uncorrelated to each other.

  2. (b)

    Incorporation of N in the gate insulator has minimal impact on ΔV IT for NBTI but significantly reduces ΔV IT-HK for PBTI stress, while N increases both ΔV HT and ΔV ET for NBTI and PBTI stress, respectively. This unequivocally indicates that the trap generation and trapping subcomponents are mutually uncorrelated. Although ΔV IT and ΔV IT-HK dominate NBTI and PBTI respectively, a relatively larger ΔV HT or ΔV ET contribution results in reduction in n for overall ΔV T in HKMG devices containing N in the gate stack.

  3. (c)

    The power-law E OX acceleration factor ΓE has been found to be identical for ΔV IT and ΔV HT (or for ΔV IT-HK and ΔV ET) and therefore for ΔV T for all HKMG processes, although ΓE reduces for devices containing N in the gate stack or with reduction in IL thickness.

  4. (d)

    The Arrhenius T activation energy E A is larger for ΔV IT (or ΔV IT-HK) compared to ΔV HT (or ΔV ET). Therefore, the relative magnitude of trap generation and trapping determines E A for overall ΔV T. HKMG processes having relatively larger trapping subcomponent show lower E A for ΔV T and vice versa.

  5. (e)

    For AC stress, ΔV IT (or ΔV IT-HK) remains independent of f but increases with increase in PDC of the gate pulse . However, the AC/DC ratio and PDC dependent shape for ΔV IT (or ΔV IT-HK) is very different from that for ΔV T, and will be explained later in the book.