Abstract
Today is the era of information explosion, efficient methods for massive data processing are becoming a hotspot. MapReduce is a popular parallel programming model and widely used in large-scale data parallel computing. This paper proposes a parallel programming model based on heterogeneous multi-core embedded processor. On the base of ordinary computer completing computing, we make optimization and improvement, and use the method of combining embedded dual-core ARM processors with multiple high performance FPGAs to complete complex processing. Xilinx Zynq device is used as the hardware platform. By selecting Sobel image processing, histogram, matrix multiply and illumination enhancement cases, we test the parallel programming model. The results show that the speedup is 84.62x versus CPU-based implementation. In addition, it is proven that this parallel programming model is suitable for the CPU-FPGA heterogeneous system which can be used as cluster cloud computing node. Meanwhile, we make a comparison of our model with other references and verify the efficient of the programming model in this paper.
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References
Dean, J., Ghemawat, S.: MapReduce: simplified data processing on large clusters. In: Sixth Symposium on Operating System Design and Implementation (OSDI), San Francisco, CA (2004)
Condie, T., Conway, N., Alvaro, P., et al.: Mapreduce online [R/OL]. 2009-10. http://www.eecs.berkeley.edu/Pubs/
Chu, C.T., Kim, S.K., Lin, Y. A., et al.: Mapreduce for machine learning on multicore. In: Advances in Neural Information Processing Systems (2007)
Li, S., Yin, D., Mu, D.: Scalable mapreduce framework design and realization base on FPGA. Comput. Technol. Dev. 22(2), 28 (2012)
He, B., Fang, W., Luo, Q., et al.: Mars: a mapreduce framework on graphics processors. In: 17th International Conference on Parallel Architectures and Compilation Techniques (2008)
Shan, Y., Wang, B., Yan, J., et al.: FPMR: mapreduce framework on FPGA. In: Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (2010)
Yeung, J.H.C., Tsang, C.C., Tsoi, K.H., et al. Map-reduce as a programming module for custom computing machines. In: IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) (2008)
Tsoi, K.H., Luk, W.: Axel: a heterogeneous cluster with FPGAs and GPUs. In: Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (2010)
High-performance-video-AXI-interconnect (2013)
DeHon, A. et al.: Design patterns for reconfigurable computing. In: Proceedings of 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines. IEEE CS Press, pp. 13–23 (2004)
Xilinx Inc. 7 series FPGAs overview (ver 1,14) (2013)
Zynq-7000 EPP Technical Reference Manual (2012)
Ranger, C., Raghuraman, R., Penmetsa, A., Bradski, G. and Kozyrakis, C.: Evaluating mapreduce for multi-core and multiprocessor systems. In: Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), Phoenix, AZ, February 2007
Zynq-7000 Extensible Processing Platform Overview (2012)
Zhang, X., Shen, P., Luo, L.: Enhancement and noise reduction of very low light level images. In: 21st International Conference on Pattern Recognition (ICPR 2012). 11–15 Nov 2012
He, K., Sun, J., Tang, X.: Signal image haze removal using dark channel prior. IEEE Trans. Pattern Anal. Mach. Intell. 33(12), 2341–2353 (2011)
Zhang, L., Ling, C.: Application of Sobel edge detection based on FPGA. Electron. Appl. Technol. 37(8), 26–29 (2011)
Xilinx Inc. Vivado high-level synthesis user guide (2012)
Singh, S., Saini, A.K., , Saini, R., et al. Area optimized FPGA-based implementation of the Sobel compass edge detector. ISRN Machine Vision (2013)
Yasri, I., Hamid, N.H., Yap, V.V.: Performance analysis of FPGA based Sobel edge detection operator. In: 2008 International Conference on Electronic Design, 1–3 Dec 2008
Donthi, S., Haggard, R.L.: A survey of dynamically reconfigurable FPGA devices. IEEE Transaction, pp 422–426, 8 March 2003
Xilinx Inc. Accelerating OpenCV application with Zynq using Vivado HLS video Libraries. 2013
Apache Hadoop, http://hadoop.apache.org/
Chu, C., Kim, S., Lin, Y., Yu, Y., Bradski, G., Ng, A.Y., Olukotun, K.: Map-reduce for machine learning on multicore. In: NIPS’07: Proceedings of Twenty-First Annual Conference on Neural Information Processing Systems. Neural Information Processing Systems Foundation (2007)
Adam Pisoni. Skynet, Apr. 2008. http://skynet.rubyforge.org
Ericson, M., Johansson, M.: A general purpose embedded system utilizing Rumime reconfiguration. In: The International Conference on Reconfigurable Computing and FPGAs ReConFig, Colima, Mexico, pp. 483–490 (2004)
Acknowledgements
The authors of this paper are members of Shanghai Engineering Research Center of Intelligent Video Surveillance. In part by nation key R&D Program of China 2017YFC0803700 and Program of Science and Technology Commission of Shanghai Municipality (No. 15530701300).
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Cai, Y., Tang, Z. (2019). A Parallel Programming Model Research Based on Heterogeneous Multi-core Embedded Processor. In: Abawajy, J., Choo, KK., Islam, R., Xu, Z., Atiquzzaman, M. (eds) International Conference on Applications and Techniques in Cyber Security and Intelligence ATCI 2018. ATCI 2018. Advances in Intelligent Systems and Computing, vol 842. Springer, Cham. https://doi.org/10.1007/978-3-319-98776-7_9
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DOI: https://doi.org/10.1007/978-3-319-98776-7_9
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