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Future generations of integrated circuit technologies are trending toward higher speeds and densities. The total capacitive load associated with the internal circuitry has been increasing for several generations of high complexity integrated circuits [149, 243]. As the operating frequencies increase, the average on-chip current required to charge and discharge these capacitances also has increased, while the switching time has decreased. As a result, a large change in the total on-chip current can occur within a brief period of time.

Due to the high slew rate of the currents flowing through the bonding wires, package pins, and on-chip interconnects, the ground and supply voltage can fluctuate (or bounce) due to the parasitic impedances associated with the package-to-chip and on-chip interconnects. These voltage fluctuations on the supply and ground rails, called ground bounce, \(\Delta \,I\) noise, or simultaneous switching noise (SSN) [118] , are larger since a significant number of the I/O drivers and internal logic circuitry switch close in time to the clock edges. SSN generates glitches on the ground and power supply wires, decreasing the effective current drive of the circuits, producing output signal distortion, thereby reducing the noise margins of a system. As a result, the performance and functionality of the system can be severely compromised.

In the past, research on SSN has concentrated on transient power noise caused by current flowing through the inductive bonding wires at the I/O buffers. SSN originating from the internal circuitry, however, has become an important issue in the design of nanoscale high performance ICs, such as systems-on-chip, mixed-signal circuits, and microprocessors. This increased importance is due to fast clock rates, large on-chip switching activities and currents, and increased on-chip inductance, all of which are increasingly common characteristics of nanoscale synchronous ICs.

Most of the work in this area falls into one of two categories: the first category includes analytic models that predict the behavior of the SSN, while the second category describes techniques to reduce ground bounce. A number of approaches have previously been described to analyze power and ground bounce and the effect of SSN on the performance of high complexity integrated circuits. Senthinathan et al. described an accurate technique for estimating the peak ground bounce noise by observing negative local feedback present in the current path of the driver [532]. This work suffers from the assumption that the switching currents of the output drivers are modeled as a triangular shape. In [533], Vaidyanath, Thoroddsen, and Prince relaxed this assumption by deriving an expression for the peak value of the ground bounce under the more realistic assumption that the ground bounce is a linear function of time during the output transition of the driver. Other research has considered short-channel effects in CMOS devices on the ground bounce waveform [534–536]. While most prior research has concentrated on the case where all of the drivers switch simultaneously, the authors in [535] consider the more realistic scenario when the drivers switch at different times. The idea of considering the effects of ground bounce on a tapered buffer has been presented in [537]. Tang and Friedman developed an analytic expression characterizing the on-chip SSN voltage based on a lumped RLC model characterizing the on-chip power supply rail rather than a single inductor to model a bonding wire [23]. In [538], Heydari and Pedram addressed ground bounce with no assumptions about the form of the switching current or noise voltage waveforms. The effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed. An analytic expression for the total propagation delay in the presence of ground bounce is also developed.

A number of techniques have been described to reduce SSN. In [539], a voltage controlled output buffer is described to control the slew rate. Ground bounce reduction is achieved by lowering the inductance in the power and ground paths by utilizing substrate conduction. An algorithm based on integer linear programming to skew the switching of the drivers to minimize ground bounce is presented in [540]. An architectural approach for reducing inductive noise caused by clock gating through gradual activation/deactivation units has been described in [541]. In [542], a routing method is described to distribute the ground bounce among the pads under a constraint of constant routing area. The total P/G noise of the system, however, is not reduced. Decoupling capacitors are often added to maintain the voltage on the P/G rails within specification, providing charge for the switching transients [538, 543]. Recently, several methods for reducing ground bounce have been suggested, such as bounce pre-generator circuits [544], supply current shaping, and clock frequency modulation [545].

Design techniques to reduce P/G noise in mixed-signal power distribution systems is the primary focus of this chapter. The efficiency of these techniques is based on the physical parameters of the system. This chapter is organized as follows. Ground noise reduction through the addition of a noise-free on-chip ground is described in Sect. 32.1. The efficiency of the technique as a function of the physical parameters of the system is evaluated in Sect. 32.2. Some specific conclusions are summarized in Sect. 32.3.

1 Ground Noise Reduction Through an Additional Low Noise On-Chip Ground

An equivalent circuit of an SoC-based power delivery system is shown in Fig. 32.1. Traditionally, noisy digital circuits share the power and ground supply with noise sensitive analog circuits (see Chap. 41). If a number of digital blocks switch simultaneously, the current I D drawn from the power distribution network can be significant. This large current passes through the parasitic resistance \(R_{\mathrm{Gnd}}^{p}\) and inductance \(L_{\mathrm{Gnd}}^{p}\) of the package, producing voltage fluctuations on the ground terminal (point A). As a result, ground bounce (or voltage fluctuations) appears at the ground terminal of the noise sensitive circuits.

Fig. 32.1
figure 1

An equivalent circuit for analyzing ground bounce in an SoC. The power distribution network is modeled as a series resistance and inductance. The superscripts p and c denote the parasitic impedance of, respectively, the package and on-chip power delivery systems. The subscript V dd denotes the power supply voltage and the superscript Gnd denotes the ground

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To reduce voltage fluctuations at the ground terminal of the noise sensitive blocks, an on-chip low noise ground is added, as shown in Fig. 32.2. This approach utilizes a voltage divider formed by the impedance between the noisy ground terminal and the quiet ground terminal and the impedance of the path from the quiet ground terminal to the off-chip ground. The value of the capacitor is chosen to cancel the parasitic inductance of the additional low noise ground, i.e., the ESL of the capacitor L d and the on-chip and package parasitic inductances of the dedicated low noise ground, respectively, \(L_{c}^{3}\) and \(L_{p}^{3}\). Alternatively, the capacitor is tuned in resonance with the parasitic inductances at a frequency that produces the greatest reduction in noise. The impedance of the additional ground path, therefore, behaves as a simple resistance.

Fig. 32.2
figure 2

Ground bounce reduction technique. The effective series resistance and effective series inductance of the decoupling capacitor are modeled by, respectively, R d and L d . \(R_{c}^{5}\) and \(L_{c}^{5}\) represent the physical separation between the noisy and noise sensitive blocks. The impedance of the additional on-chip ground is modeled by, respectively, \(R_{c}^{3}\) and \(L_{c}^{3}\)

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The same technique can be used to reduce voltage fluctuations on the power supply. Based on the nature of the power supply noise, an additional ground path or power supply path can be provided. For instance, to ensure that the voltage does not drop below the power supply level, an on-chip path to the power supply is added. In the case of an overshoot, an additional ground path can be provided.

2 Dependence of Ground Bounce Reduction on System Parameters

To determine the efficiency in reducing ground bounce, a simplified circuit model of the technique is used, as shown in Fig. 32.3. The ground bounce caused by simultaneously switching within the digital circuitry is modeled as a voltage source. A sinusoidal voltage source with an amplitude of 100 mV is used to determine the reduction in ground bounce at a single frequency. A triangular voltage source with an amplitude of 100 mV, rise time of 50 ps, and fall time of 200 ps is utilized to estimate the reduction in ground noise.

Fig. 32.3
figure 3

Simplified circuit of the ground bounce reduction technique. The ground bounce due to simultaneously switching the digital circuits is modeled by a voltage source. The Noisy Gnd denotes an on-chip ground for the simultaneously switching digital circuits. The Quiet Gnd denotes a low noise ground for the noise sensitive circuits

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The dependence of the noise reduction technique on the physical separation between the noisy and noise sensitive circuits is presented in Sect. 32.2.1. The sensitivity of this technique to frequency and capacitance variations is discussed in Sect. 32.2.2. The dependence of ground noise on the impedance of an additional on-chip ground path is analyzed in Sect. 32.2.3.

2.1 Physical Separation Between Noisy and Noise Sensitive Circuits

To determine the dependence of the noise reduction technique on the physical separation between the noise source and noise receiver, the impedance of the ground path between the noisy and quiet terminals is modeled as a series RL, composed of the parasitic resistance and inductance per unit length. The peak voltage at the quiet ground is evaluated using SPICE where the distance between the digital and analog circuits is varied from one to ten unit lengths. The reduction in ground bounce as seen from the ground terminal of the noise sensitive circuit for sinusoidal and triangular noise sources is listed in Table 32.1.

Table 32.1 Ground bounce reduction as a function of the separation between the noisy and noise sensitive circuits
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Note that the reduction in ground noise increases linearly as the physical separation between the noisy and noise sensitive circuits becomes greater. A reduction in ground bounce of about 52 % for a single frequency noise source and about 16 % for a random noise source is achieved for a ground line (of ten unit lengths) between the digital and analog blocks. Enhanced results can be achieved if the impedance of the additional ground is much smaller than the impedance of the interconnect between the noisy and noise sensitive modules. From a circuits perspective, the digital and analog circuits should be placed sufficiently distant and the additional low noise ground should be composed of multiple parallel lines. Moreover, the additional ground should be placed close to the multiple ground pins.

Note that since this noise reduction technique utilizes a capacitor tuned in resonance with the parasitic inductance of an additional ground path, this approach is frequency dependent and produces the best results for a single frequency noise source. In the case of a random noise source, the frequency harmonic with the highest magnitude should be significantly reduced, thereby achieving the greatest reduction in noise. For example, the second harmonic is selected in the case of a triangular noise source.

2.2 Frequency and Capacitance Variations

To determine the sensitivity of the ground bounce reduction technique on frequency and capacitance variations, the frequency is varied by ±50 % from the resonant frequency and the capacitor is varied by ±10 % from the target value. The range of capacitance variation is chosen based on typical process variations for a CMOS technology. The efficiency of the reduction in ground bounce for a sinusoidal noise source versus frequency and capacitance variations is illustrated, respectively, in Figs. 32.4 and 32.5.

Fig. 32.4
figure 4

Ground bounce reduction as a function of noise frequency. The reduction in noise drops linearly as the frequency varies from the target resonant frequency. The ground noise is modeled as a sinusoidal voltage source

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Fig. 32.5
figure 5

Reduction in ground bounce as a function of capacitance variations. The reduction in ground bounce is almost insensitive to capacitance variations. The ground bounce is modeled as a sinusoidal voltage source

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Note that the noise reduction drops linearly as the noise frequency varies from the target resonant frequency. The reduction in noise is slightly greater for higher frequencies. This phenomenon is due to the uncompensated parasitic inductance of the ground connecting the digital circuits to the analog circuits. As a result, at higher frequencies, the impedance of the ground path of a power delivery network increases, further reducing the noise. In general, the technique results in lower noise at higher frequencies. As illustrated in Fig. 32.5, the reduction in ground bounce is almost insensitive to capacitance variations. The efficiency of the technique drops by about 4 % as the capacitance is varied by ±10 %.

2.3 Impedance of an Additional Ground Path

As described in Sect. 32.1, the noise reduction technique utilizes a voltage divider formed by the ground of an on-chip power distribution system and an additional low noise ground. To increase the efficiency of the technique, the voltage transfer function of the voltage divider should be lowered, permitting a greater portion of the noise voltage to be diverted through the additional ground. As demonstrated in Sect. 32.2.1, placing the noisy and noise sensitive blocks farther from each other lowers the bounce at the ground terminal of the analog circuits. The ground noise can also be reduced by lowering the impedance of the low noise ground. The parasitic inductance of the additional ground is canceled by the capacitor tuned in resonance to the specific frequency. The impedance of the additional ground is therefore purely resistive at the resonant frequency. The reduction in noise for different values of the parasitic resistance of the low noise ground is listed in Table 32.2.

Table 32.2 Ground bounce reduction for different values of parasitic resistance of the on-chip low noise ground
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Note from Table 32.2 that by reducing the parasitic resistance of an on-chip low noise ground, the ground bounce can be significantly lowered. Noise reductions of about 68 % and 22 % are demonstrated for, respectively, sinusoidal and triangular noise sources. The results listed in Table 32.2 are determined for an average resistance and inductance of the on-chip power distribution ground of five unit lengths (see Table 32.1). Thus, the ground bounce can be further reduced if the analog and digital circuits are placed farther from each other. Even better results can be achieved if the parasitic resistance of the package pins \(R_{p}^{3}\) and decoupling capacitor R d are lowered. From a circuits perspective, the low noise on-chip ground should be composed of many narrow lines connected in parallel to lower the parasitic resistance and inductance. A number of package pins should therefore be dedicated to the noise-free ground to lower the package resistance. A decoupling capacitor with a low ESR is also recommended.

3 Summary

Design techniques to reduce ground bounce in SoC and mixed-signal ICs are presented in this chapter and can be summarized as follows.

  • A noise reduction technique with an additional on-chip ground is described to divert ground noise from the sensitive analog circuits

  • The technique utilizes a decoupling capacitor tuned in resonance with the parasitic inductance of an additional low noise ground, making the technique frequency dependent

  • The reduction in ground bounce, however, is almost independent of capacitance variations

  • Noise reductions of 68 % and 22 % are demonstrated for, respectively, a single frequency and random ground noise

  • The noise reduction efficiency can be further enhanced by simultaneously lowering the impedance of the additional noise-free ground and increasing the impedance of the ground path between the digital (noisy) and analog (noise sensitive) circuits