Efficient Placement of Distributed On-Chip Decoupling Capacitors

Abstract

Decoupling capacitors are widely used to manage power supply noise [281] and are an effective way to reduce the impedance of power delivery systems operating at high frequencies [28, 29]. A decoupling capacitor acts as a local reservoir of charge, which is released when the power supply voltage at a particular current load drops below some tolerable level. Since the inductance scales slowly [129], the location of the decoupling capacitors significantly affects the design of the power/ground networks in high performance integrated circuits such as microprocessors. At higher frequencies, a distributed system of decoupling capacitors are placed on-chip to effectively manage the power supply noise [279].

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Decoupling capacitors are widely used to manage power supply noise [281] and are an effective way to reduce the impedance of power delivery systems operating at high frequencies [28, 29]. A decoupling capacitor acts as a local reservoir of charge, which is released when the power supply voltage at a particular current load drops below some tolerable level. Since the inductance scales slowly [129], the location of the decoupling capacitors significantly affects the design of the power/ground networks in high performance integrated circuits such as microprocessors. At higher frequencies, a distributed system of decoupling capacitors are placed on-chip to effectively manage the power supply noise [279].

The efficacy of decoupling capacitors depends upon the impedance of the conductors connecting the capacitors to the current loads and power sources. As described in [277], a maximum parasitic impedance between the decoupling capacitor and the current load (or power source) exists at which the decoupling capacitor is effective. Alternatively, to be effective, an on-chip decoupling capacitor should be placed such that both the power supply and the current load are located inside the appropriate effective radius [277] . The efficient placement of on-chip decoupling capacitors in nanoscale ICs is the subject of this chapter. Unlike the methodology for placing a single lumped on-chip decoupling capacitor presented in Chap. 12, a system of distributed on-chip decoupling capacitors is described in this chapter. A design methodology to estimate the parameters of the distributed system of on-chip decoupling capacitors is also presented, permitting the required on-chip decoupling capacitance to be allocated under existing technology constraints.

This chapter is organized as follows. Technology limitations in nanoscale integrated circuits are reviewed in Sect. 13.1. The problem of placing on-chip decoupling capacitors in nanoscale ICs while satisfying technology constraints is formulated in Sect. 13.2. The design of a distributed on-chip decoupling capacitor network is presented in Sect. 13.3. Various design tradeoffs are discussed in Sect. 13.4. A design methodology for placing distributed on-chip decoupling capacitors is presented in Sect. 13.5. Related simulation results for typical values of on-chip parasitic resistances are discussed in Sect. 13.6. Some specific conclusions are summarized in Sect. 13.7.

1 Technology Constraints

On-chip decoupling capacitors have traditionally been designed as standard gate oxide CMOS capacitors [288] . As technology scales, leakage current through the gate oxide of an on-chip decoupling capacitor has greatly increased [289–291]. Moreover, in modern high performance ICs, a large portion (up to 40 %) of the circuit area is occupied by the on-chip decoupling capacitance [292, 293]. Conventional gate oxide on-chip decoupling capacitors are therefore prohibitively expensive from an area and yield perspective, as well as greatly increasing the overall power dissipated on-chip [294].

To reduce the power consumed by an IC, MIM capacitors are frequently utilized as decoupling capacitors. The capacitance density of a MIM capacitor in a 90 nm CMOS technology is comparable to the maximum capacitance density of a CMOS capacitor and is typically 10–30 fF/μm² [256, 259, 270]. A maximum magnitude of an on-chip decoupling capacitor therefore exists for a specific distance between a current load and a decoupling capacitor (as constrained by the available on-chip metal resources). Alternatively, a minimum achievable impedance per unit length exists for a specified capacitance density of an on-chip decoupling capacitor placed at a specific distance from a circuit module, as illustrated in Fig. 13.1.

Fig. 13.1

Fundamental limits of on-chip interconnections. Two levels of a distributed on-chip decoupling capacitance are allocated around a current load. The interconnect impedance is inversely proportional to the fraction of metal area dedicated to the interconnect level, decreasing as the decoupling capacitor is farther from the current source (Z ₁ > Z ₂). The decoupling capacitance increases as the capacitor is farther from the current load due to the increased area (C ₁ < C ₂). The two levels of interconnection and distributed decoupling capacitance are shown, respectively, in dark pink and light pink

Observe from Fig. 13.1 that the available metal area for the second level of a distributed on-chip capacitance is greater than the fraction of metal resources dedicated to the first level of a distributed on-chip capacitance. Capacitor C ₂ can therefore be larger than C ₁. Note also that a larger capacitor can only be placed farther from the current load. Similarly, the metal resources required by the first level of interconnection (connecting C ₁ to the current load) is smaller than the metal resources dedicated to the second level of interconnections. The impedance Z ₂ is therefore smaller than Z ₁.

2 Placing On-Chip Decoupling Capacitors in Nanoscale ICs

Decoupling capacitors have traditionally been allocated into the white space (those areas not occupied by the circuit elements) available on the die based on an unsystematic or ad hoc approach [283, 284], as shown in Fig. 13.2. In this way, decoupling capacitors are often placed at a significant distance from the current load. Conventional approaches for placing on-chip decoupling capacitors result in oversized capacitors. The conventional allocation strategy, therefore, results in increased power noise, compromising the signal integrity of an entire system, as illustrated in Fig. 13.3. This issue of power delivery cannot be alleviated by simply increasing the size of the on-chip decoupling capacitors. Furthermore, increasing the size of more distant on-chip decoupling capacitors results in wasted area, increased power, reduced reliability , and higher cost. A design methodology is therefore required to account for technology trends in nanoscale ICs, such as increasing frequencies, larger die sizes, higher current demands, and reduced noise margins.

Fig. 13.2

Placement of on-chip decoupling capacitors using a conventional approach. Decoupling capacitors are allocated into the white space (those areas not occupied by the circuits elements) available on the die using an unsystematic or ad hoc approach. As a result, the power supply voltage drops below the minimum tolerable level for remote blocks (shown in dark gray). Low noise regions are light gray

Fig. 13.3

A conventional on-chip decoupling capacitor. Typically, a large decoupling capacitor is placed farther from the current load due to physical limitations. Current flowing through the long power/ground lines results in large voltage fluctuations across the terminals of the current load

To be effective, a decoupling capacitor should be placed physically close to the current load. This requirement is naturally satisfied in board and package applications, since large capacitors are much smaller than the dimensions of the circuit board (or package) [223]. In this case, a lumped model of a decoupling capacitor provides sufficient accuracy [295].

The size of an on-chip decoupling capacitor, however, is directly proportional to the area occupied by the capacitor and can require a significant portion of the on-chip area. The minimum impedance between an on-chip capacitor and the current load is fundamentally affected by the magnitude (and therefore the area) of the capacitor. Systematically partitioning the decoupling capacitor into smaller capacitors solves this issue. A system of distributed on-chip decoupling capacitors is illustrated in Fig. 13.4.

Fig. 13.4

A network of distributed on-chip decoupling capacitors. The magnitude of the decoupling capacitors is based on the impedance of the interconnect segment connecting a specific capacitor to a current load. Each decoupling capacitor is designed to only provide charge during a specific time interval

In a system of distributed on-chip decoupling capacitors , each decoupling capacitor is sized based on the impedance of the interconnect segment connecting the capacitor to the current load. A particular capacitor only provides charge to a current load during a short period. The rationale behind this scheme can be explained as follows. The capacitor closest to the current load is engaged immediately after the switching cycle is initiated. Once the first capacitor is depleted of charge, the next capacitor is activated, providing a large portion of the total current drawn by the load. This procedure is repeated until the last capacitor becomes active. Similar to the hierarchical placement of decoupling capacitors presented in [28, 136], this technique provides an efficient solution for providing the required on-chip decoupling capacitance based on specified capacitance density constraints. A system of distributed on-chip decoupling capacitors should therefore be utilized to provide a low impedance, cost effective power delivery network in nanoscale ICs.

3 Design of a Distributed On-Chip Decoupling Capacitor Network

As described in Sect. 13.2, a system of distributed on-chip decoupling capacitors is an efficient solution for providing the required on-chip decoupling capacitance based on the maximum capacitance density available in a particular technology. A physical model of the technique is illustrated in Fig. 13.5. For simplicity, two decoupling capacitors are assumed to provide the required charge drawn by the current load. Note that as the capacitor is placed farther from the current load, the magnitude of an on-chip decoupling capacitor increases due to relaxed constraints. In the general case, the described methodology can be extended to any practical number of on-chip decoupling capacitors. Note that Z ₁ is typically limited by a specific technology (determined by the impedance of a single metal wire) and the magnitude of C ₁ (the area available in the vicinity of a circuit block).

Fig. 13.5

A physical model of a system of distributed on-chip decoupling capacitors. Two capacitors are assumed to provide the required charge drawn by the load. Z ₁ and Z ₂ denote the impedance of the metal lines connecting, respectively, C ₁ to the current load and C ₂ to C ₁

A circuit model of a system of distributed on-chip decoupling capacitors is shown in Fig. 13.6. The impedance of the metal lines connecting the capacitors to the current load is modeled as resistors R ₁ and R ₂. A triangular current source is assumed to model the current load. The magnitude of the current source increases linearly, reaching the maximum current I _max at rise time t _r , i.e., $I_{load}(t) = I_{\mathrm{max}} \frac{t} {t_{r}}$. The maximum tolerable ripple at the load is 10 % of the power supply voltage.

Fig. 13.6

A circuit model of an on-chip distributed decoupling capacitor network. The impedance of the metal lines is modeled, respectively, as R ₁ and R ₂

Note from Fig. 13.6 that since the charge drawn by the current load is provided by the on-chip decoupling capacitors, the voltage across the capacitors during discharge drops below the initial power supply voltage. The required charge during the entire switching event is thus determined by the voltage drop across C ₁ and C ₂.

The voltage across the decoupling capacitors at the end of the switching cycle (t = t _r ) can be determined from Kirchhoff’s laws [287]. Writing KVL and KCL equations for each of the loops (see Fig. 13.6), the system of differential equations describing the voltage across C ₁ and C ₂ at t _r is

$$\displaystyle{ \frac{dV _{C_{1}}} {dt} = \frac{V _{C_{2}} - V _{C_{1}}} {R_{2}C_{1}} -\frac{I_{load}} {C_{1}}, }$$

(13.1)

$$\displaystyle{ \frac{dV _{C_{2}}} {dt} = \frac{V _{C_{1}} - V _{C_{2}}} {R_{2}C_{2}}. }$$

(13.2)

Simultaneously solving (13.1) and (13.2) and applying the initial conditions, the voltage across C ₁ and C ₂ at the end of the switching activity is

$$\displaystyle\begin{array}{rcl} V _{C_{1}}\vert _{t=t_{r}}& =& \frac{1} {2(C_{1} + C_{2})^{3}t_{r}}\bigg[2C_{1}^{3}t_{ r} + C_{1}^{2}t_{ r}(6C_{2} - I_{\mathrm{max}}t_{r}) \\ & & -C_{2}^{2}t_{ r}\left (2C_{2}\left (I_{\mathrm{max}}R_{2} - 1\right ) + I_{\mathrm{max}}t_{r}\right ) \\ & & +2C_{1}C_{2}\left (C_{2}^{2}\left (1 - e^{-\frac{(C_{1}+C_{2})t_{r}} {C_{1}C_{2}R_{2}} }\right )I_{\mathrm{max}}R_{2}^{2}\right. \\ & & +C_{2}\left (3 - I_{\mathrm{max}}R_{2}\right )t_{r} - I_{\mathrm{max}}t_{r}^{2}\bigg)\bigg], {}\end{array}$$

(13.3)

$$\displaystyle\begin{array}{rcl} V _{C_{2}}\vert _{t=t_{r}}& =& \frac{1} {2(C_{1} + C_{2})^{3}t_{r}}\bigg[2C_{1}^{3}t_{ r} + C_{2}^{2}t_{ r}\left (2C_{2} - I_{\mathrm{max}}t_{r}\right ) \\ & & +2C_{1}C_{2}t_{r}\left (C_{2}\left (3 + I_{\mathrm{max}}R_{2}\right ) - I_{\mathrm{max}}t_{r}\right ) \\ & & +C_{1}^{2}\left (2C_{ 2}^{2}\left (e^{-\frac{(C_{1}+C_{2})t_{r}} {C_{1}C_{2}R_{2}} } - 1\right )I_{\mathrm{max}}R_{2}^{2}\right. \\ & & +2C_{2}\left (3 + I_{\mathrm{max}}R_{2}\right )t_{r} - I_{\mathrm{max}}t_{r}^{2}\bigg)\bigg], {}\end{array}$$

(13.4)

where I _max is the maximum magnitude of the current load and t _r is the rise time.

Note that the voltage across C ₁ and C ₂ after discharge is determined by the magnitude of the decoupling capacitors and the parasitic resistance of the metal line(s) between the capacitors. The voltage across C ₁ after the switching cycle, however, depends upon the resistance of the P/G paths connecting C ₁ to a current load and is

$$\displaystyle{ V _{C_{1}} = V _{load} + I_{\mathrm{max}}R_{1}, }$$

(13.5)

where V _load is the voltage across the terminals of a current load. Assuming V _load  ≥ 0. 9V _dd and $V _{C_{1}}^{\mathrm{max}} = V _{\mathrm{ dd}}$ (meaning that C ₁ is infinitely large), the upper bound for R ₁ is

$$\displaystyle{ R_{1}^{\mathrm{max}} = \frac{V _{\mathrm{dd}}(1-\alpha )} {I_{\mathrm{max}}}, }$$

(13.6)

where α is the ratio of the minimum tolerable voltage across the terminals of a current load to the power supply voltage (α = 0. 9 in this chapter). If R ₁ > R ₁ ^max, no solution exists for providing sufficient charge drawn by the load. In this case, the circuit block should be partitioned, reducing the current demands (I _max).

Note that expressions for determining the voltage across the decoupling capacitors are transcendental functions. No closed-form solution, therefore, exists. From (13.3) and (13.4), the design space can be graphically obtained for determining the maximum tolerable resistance R ₂ and the minimum magnitude of the capacitors, maintaining the voltage across the load equal to or greater than the minimum allowable level. The voltage across C ₁ after discharge as a function of C ₁ and R ₂ is depicted in Fig. 13.7.

Fig. 13.7

Voltage across C ₁ during discharge as a function of C ₁ and R ₂: I _max = 0. 01 mA, V _dd = 1 V, and t _r  = 100 ps; (a) assuming C ₁ = C ₂ and R ₁ = 10 Ω, the minimum tolerable voltage across C ₁, resulting in V _load  ≥ 0. 9V _dd, is 0.91 V (shown as a black equipotential line), (b) design space for determining C ₁ and R ₂ resulting in the voltage across C ₁ equal to 0.91 V

Observe from Fig. 13.7 that the voltage across capacitor C ₁ increases exponentially with capacitance, saturating for large C ₁. The voltage across C ₁, however, is almost independent of R ₂, decreasing slightly with R ₂ (see Fig. 13.7a). This behavior can be explained as follows. As a current load draws charge from the decoupling capacitors, the voltage across the capacitors drops below the initial level. The charge released by a capacitor is proportional to the capacitance and the change in voltage. A larger capacitance therefore results in a smaller voltage drop. From Fig. 13.6, note that as resistance R ₂ increases, capacitor C ₂ becomes less effective (a larger portion of the total current is provided by C ₁). As a result, the magnitude of C ₁ is increased to maintain the voltage across the load above the minimum tolerable level. Similarly, a larger C ₂ results in a smaller C ₁. As C ₂ is increased, a larger portion of the total current is provided by C ₂, reducing the magnitude of C ₁. This phenomenon is well pronounced for small R ₂, diminishing with larger R ₂, as illustrated in Fig. 13.7b.

In general, to determine the parameters of the system of distributed on-chip decoupling capacitors, the following assumptions are made. The parasitic resistance of the metal line(s) connecting capacitor C ₁ to the current load is known. R ₁ is determined by technology constraints (the sheet resistance) and by design constraints (the maximum available metal resources). The minimum voltage level at the load is V _load  = 0. 9V _dd. The maximum magnitude of the current load I _max is 0.01 A, the rise time t _r is 100 ps, and the power supply voltage V _dd is 1 V. Note that the voltage across C ₂ after discharge as determined by (13.4) is also treated as a design parameter. Since the capacitor C ₂ is directly connected to the power supply (a shared power rail), the voltage drop across C ₂ appears on the global power line, compromising the signal integrity of the overall system. The voltage across C ₂ at t _r is therefore based on the maximum tolerable voltage fluctuations on the P/G line during discharge (the voltage across C ₂ at the end of the switching cycle is set to 0.95 V).

The system of equations to determine the parameters of an on-chip distributed decoupling capacitor network as depicted in Fig. 13.6 is

$$\displaystyle{ V _{load} = V _{C_{1}} - I_{\mathrm{max}}R_{1}, }$$

(13.7)

$$\displaystyle{ V _{C_{1}} = f(C_{1},C_{2},R_{2}), }$$

(13.8)

$$\displaystyle{ V _{C_{2}} = f(C_{1},C_{2},R_{2}), }$$

(13.9)

$$\displaystyle{ \frac{I_{\mathrm{max}}t_{r}} {2} = C_{1}\left (V _{\mathrm{dd}} - V _{C_{1}}\right ) + C_{2}\left (V _{\mathrm{dd}} - V _{C_{2}}\right ), }$$

(13.10)

where $V _{C_{1}}$ and $V _{C_{2}}$ are the voltage across C ₁ and C ₂ and determined, respectively, by (13.3) and (13.4). Equation (13.10) states that the total charge drawn by the current load is provided by C ₁ and C ₂. Note that in the general case with the current load determined a priori, the total charge is the integral of I _load (t) from zero to t _r . Solving (13.7) for $V _{C_{1}}$ and substituting into (13.8), C ₁, C ₂, and R ₂ are determined from (13.8), (13.9), and (13.10) for a specified $V _{C_{2}}(t_{r})$, as discussed in the following section.

4 Design Tradeoffs in a Distributed On-Chip Decoupling Capacitor Network

To design a system of distributed on-chip decoupling capacitors, the parasitic resistances and capacitances should be determined based on design and technology constraints. As shown in Sect. 13.3, in a system composed of two decoupling capacitors (see Fig. 13.6) with known R ₁; R ₂, C ₁, and C ₂ are determined from the system of Eqs. (13.7), (13.8), (13.9) and (13.10). Note that since this system of equations involves transcendental functions, a closed-form solution cannot be determined. To determine the system parameters, the system of Eqs. (13.7), (13.8), (13.9) and (13.10) is solved numerically [296].

Various tradeoff scenarios are discussed in this section. The dependence of the system parameters on R ₁ is presented in Sect. 13.4.1. The design of a distributed on-chip decoupling capacitor network with the minimum magnitude of C ₁ is discussed in Sect. 13.4.2. The dependence of C ₁ and C ₂ on the parasitic resistance of the metal lines connecting the capacitors to the current load is presented in Sect. 13.4.3. The minimum total budgeted on-chip decoupling capacitance is also determined in this section.

4.1 Dependence of System Parameters on R ₁

The parameters of a distributed on-chip decoupling capacitor network for typical values of R ₁ are listed in Table 13.1. Note that the minimum magnitude of R ₂ exists for which the parameters of the system can be determined. If R ₂ is sufficiently small, the distributed decoupling capacitor network degenerates to a system with a single capacitor (where C ₁ and C ₂ are combined). For the parameters listed in Table 13.1, the minimum magnitude of R ₂ is 4 Ω, as determined from numerical simulations.

Table 13.1 Dependence of the parameters of a distributed on-chip decoupling capacitor network on R ₁

Note that the parameters of a distributed on-chip decoupling capacitor network are determined by the parasitic resistance of the P/G line(s) connecting C ₁ to the current load. As R ₁ increases, the capacitor C ₁ increases substantially (see Table 13.1). This increase in C ₁ is due to R ₁ becoming comparable to R ₂, and C ₁ providing a greater portion of the total current. Alternatively, the system of distributed on-chip decoupling capacitors degenerates to a single oversized capacitor. The system of distributed on-chip decoupling capacitors should therefore be carefully designed. Since the distributed on-chip decoupling capacitor network is strongly dependent upon the first level of interconnection (R ₁), C ₁ should be placed as physically close as possible to the current load, reducing R ₁. If such an allocation is not practically possible, the current load should be partitioned, permitting an efficient allocation of the distributed on-chip decoupling capacitors under specific technology constraints.

4.2 Minimum C ₁

In practical applications, the size of C ₁ (the capacitor closest to the current load) is typically limited by technology constraints, such as the maximum capacitance density and available area. The magnitude of the first capacitor in the distributed system is therefore typically small. In this section, the dependence of the distributed on-chip decoupling capacitor network on R ₁ is determined for minimum C ₁. A target magnitude of 1 pF is assumed for C ₁. The parameters of a system of distributed on-chip decoupling capacitors as a function of R ₁ under the constraint of a minimum C ₁ are listed in Table 13.2. Note that $V _{C_{2}}$ denotes the voltage across C ₂ after discharge.

Table 13.2 Distributed on-chip decoupling capacitor network as a function of R ₁ under the constraint of a minimum C ₁

Note that two scenarios are considered in Table 13.2 to evaluate the dependence of a distributed system of on-chip decoupling capacitors on R ₁ and R ₂. In the first scenario, the distributed on-chip decoupling capacitor network is designed to maintain the minimum tolerable voltage across the terminals of a current load. In this case, the magnitude of C ₂ increases with R ₁, becoming impractically large for large R ₂. In the second scenario, an additional constraint (the voltage across C ₂) is applied to reduce the voltage fluctuations on the shared P/G lines. In this case, as R ₁ increases, C ₂ slightly increases. In order to satisfy the constraint for $V _{C_{2}}$, R ₂ should be significantly reduced for large values of R ₁, meaning that the second capacitor should be placed close to the first capacitor. As R ₁ is further increased, R ₂ becomes negligible, implying that capacitors C ₁ and C ₂ should be merged to provide the required charge to the distant current load. Alternatively, the system of distributed on-chip decoupling capacitors degenerates to a conventional scheme with a single oversized capacitor [297].

Note that simultaneously satisfying both the voltage across the terminals of the current load and the voltage across the last decoupling capacitor is not easy. The system of on-chip distributed decoupling capacitors in this case depends upon the parameters of the first decoupling stage (R ₁ and C ₁). If C ₁ is too small, no solution exists to satisfy V _load ^min and $V _{C_{2}}^{\mathrm{min}}$. Sufficient circuit area should therefore be allocated for C ₁ early in the design process to provide the required on-chip decoupling capacitance in order to satisfy specific design and technology constraints.

4.3 Minimum Total Budgeted On-Chip Decoupling Capacitance

As discussed in Sect. 13.4.1 and 13.4.2, the design of a system of distributed on-chip decoupling capacitors is greatly determined by the parasitic resistance of the metal lines connecting C ₁ to the current load and by the magnitude of C ₁. Another important design constraint is the total budgeted on-chip decoupling capacitance. Excessive on-chip decoupling capacitance results in increased circuit area and greater leakage currents. Large on-chip decoupling capacitors can also compromise the reliability of the overall system, creating a short circuit between the plates of a capacitor [294]. It is therefore important to reduce the required on-chip decoupling capacitance while providing sufficient charge to support expected current demands.

To estimate the total required on-chip decoupling capacitance, $C_{total} = C_{1} + C_{2}$ is plotted as a function of R ₁ and R ₂, as depicted in Fig. 13.8. Note that if R ₂ is large, C ₂ is ineffective and the system of distributed on-chip decoupling capacitors behaves as a single capacitor. Observe from Fig. 13.8 that C _total increases with R ₁ for large R ₂. In this case, C ₁ is oversized, providing most of the required charge. C ₁ should therefore be placed close to the current load to reduce the total required on-chip decoupling capacitance.

Fig. 13.8

The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R ₁ and R ₂: I _max = 10 mA, V _dd = 1 V, V _load  = 0. 9 V, and t _r  = 100 ps. In the system of distributed on-chip decoupling capacitors, an optimal ratio $\frac{R_{2}} {R_{1}}$ exists, resulting in the minimum total budgeted on-chip decoupling capacitance

Similarly, if R ₂ is reduced with small R ₁, C ₂ provides most of the charge drawn by the current load. The distributed on-chip decoupling capacitor network degenerates to a conventional system with a single capacitor. As R ₁ increases, however, the total required on-chip decoupling capacitance decreases, reaching the minimum (see Fig. 13.8 for R ₁ = 3 Ω and R ₂ = 4 Ω). In this case, C ₁ and C ₂ each provide an equal amount of the total charge. As R ₁ is further increased (C ₁ is placed farther from the current load), C ₁ and C ₂ increase substantially to compensate for the increased voltage drop across R ₁. In the system of distributed on-chip decoupling capacitors, an optimal ratio $\frac{R_{2}} {R_{1}}$ exists which requires the minimum total budgeted on-chip decoupling capacitance.

Note that in the previous scenario, the magnitude of the on-chip decoupling capacitors has not been constrained. In practical applications, however, the magnitude of the first decoupling capacitor (placed close to the current load) is limited. To determine the dependence of the total required on-chip decoupling capacitance under the magnitude constraint of C ₁, C ₁ is fixed and set to 1 pF. $C_{total} = C_{1} + C_{2}$ is plotted as a function of R ₁ and R ₂, as shown in Fig. 13.9. In contrast to the results depicted in Fig. 13.8, the total budgeted on-chip decoupling capacitance required to support expected current demands increases with R ₁ and R ₂. Alternatively, C ₂ provides the major portion of the total charge. Thus, the system behaves as a single distant on-chip decoupling capacitor. In this case, C ₁ is too small. A larger area should therefore be allocated for C ₁, resulting in a balanced system with a reduced total on-chip decoupling capacitance. Also note that as R ₁ and R ₂ further increase (beyond 4 Ω, see Fig. 13.9), the total budgeted on-chip decoupling capacitance increases rapidly, becoming impractically large.

Fig. 13.9

The total budgeted on-chip decoupling capacitance as a function of the parasitic resistance of the metal lines, R ₁ and R ₂: I _max = 10 mA, V _dd = 1 V, V _load  = 0. 9 V, and t _r  = 100 ps. C ₁ is fixed and set to 1 pF. The total budgeted on-chip decoupling capacitance increases with R ₁ and R ₂. As the parasitic resistance of the metal lines is further increased beyond 4 Ω, C _total increases substantially, becoming impractically large

Comparing Figs. 13.8 and 13.9, note that if C ₁ is constrained, a larger total decoupling capacitance is required to provide the charge drawn by the current load. Alternatively, the system of distributed on-chip decoupling capacitors under a magnitude constraint of C ₁ behaves as a single distant decoupling capacitor. As a result, the magnitude of a single decoupling capacitor is significantly increased to compensate for the IR voltage drop across R ₁ and R ₂. The system of distributed on-chip decoupling capacitors should therefore be carefully designed to reduce the total budgeted on-chip decoupling capacitance. If the magnitude of C ₁ is limited, C ₂ should be placed close to the current load to be effective, reducing the total required on-chip decoupling capacitance. Alternatively, the parasitic impedance of the P/G lines connecting C ₁ and C ₂ should be reduced (e.g., utilizing wider lines and/or multiple lines in parallel) [73].

5 Design Methodology for a System of Distributed On-Chip Decoupling Capacitors

An overall methodology for designing a distributed system of on-chip decoupling capacitors is illustrated in Fig. 13.10. General differential equations for voltages $V _{C_{1}}(t)$ and $V _{C_{2}}(t)$ across capacitors C ₁ and C ₂ are derived based on Kirchhoff’s laws. The maximum parasitic resistance R ₁ ^max between C ₁ and the current load is determined from (13.6) for specific parameters of the system, such as the power supply voltage V _dd, the minimum voltage across the terminals of the current load V _load , the maximum magnitude of the current load I _max, and the rise time t _r . If R ₁ > R ₁ ^max, no solution exists for the system of distributed on-chip decoupling capacitors. Alternatively, the voltage across the terminals of a current load always drops below the minimum acceptable level. In this case, the current load should be partitioned to reduce I _max, resulting in R ₁ < R ₁ ^max.

Fig. 13.10

Design flow for determining the parameters of a system of distributed on-chip decoupling capacitors

Simultaneously solving (13.1) and (13.2), the voltage across C ₁ and C ₂ is estimated at the end of a switching cycle (t = t _r ), as determined by (13.3) and (13.4). The parameters of the distributed on-chip decoupling capacitor network C ₁, C ₂, and R ₂, are determined from (13.7), (13.8), (13.9) and (13.10). Note that different tradeoffs exist in a system of distributed on-chip decoupling capacitors, as discussed in Sect. 13.4. If the voltage across the terminals of a current load drops below the minimum tolerable level, the total budgeted on-chip decoupling capacitance should be increased. The system of Eqs. (13.7), (13.8), (13.9) and (13.10), is solved for an increased total on-chip decoupling capacitance, resulting in different C ₁, C ₂, and R ₂ until the criterion for the maximum tolerable power noise V _load  > V _load ^min is satisfied, as shown in Fig. 13.10.

Note that the system of distributed on-chip decoupling capacitors permits the design of an effective power distribution system under specified technology constraints. The techniques presented in this chapter are also applicable to future technology generations. The methodology also provides a computationally efficient way to determine the required on-chip decoupling capacitance to support expected current demands. In the worst case example presented in this chapter, the simulation time to determine the parameters of the system of on-chip distributed decoupling capacitors is under one second on a Pentium III PC with one gigabyte of RAM. A methodology for efficiently placing on-chip decoupling capacitors can also be integrated into a standard IC design flow. In this way, the circuit area required to allocate on-chip decoupling capacitors is estimated early in the design process, significantly reducing the number of iterations and the eventual time to market.

6 Case Study

The dependence of the system of distributed on-chip decoupling capacitors on the current load and the parasitic impedance of the power delivery system is described in this section to quantitatively illustrate the previously presented concepts. Resistive power and ground lines are assumed to connect the decoupling capacitors to the current load and are modeled as resistors (see Fig. 13.6). The load is modeled as a ramp current source with a 100 ps rise time. The minimum tolerable voltage across the load terminals is 90 % of the power supply. The magnitude of the on-chip decoupling capacitors for various parasitic resistances of the metal lines connecting the capacitors to the current load is listed in Table 13.3. The parameters of the distributed on-chip decoupling capacitor network listed in Table 13.3 are determined for two amplitudes of the current load. Note that the values of R ₁ and R ₂ are typical parasitic resistances of an on-chip power distribution grid for a 90 nm CMOS technology.

Table 13.3 The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load

The parameters of the system of distributed on-chip decoupling capacitors are analytically determined from (13.7), (13.8), (13.9) and (13.10). The resulting power supply noise is estimated using SPICE and compared to the maximum tolerable level (the minimum voltage across the load terminals V _load ^min). The maximum voltage drop across C ₂ at the end of the switching activity is also estimated and compared to $V _{C_{2}}^{\mathrm{min}}$. Note that the analytic solution produces an accurate estimate of the on-chip decoupling capacitors for typical parasitic resistances of a power distribution grid. The maximum error in this case study is 0.003 %.

From Table 13.3, note that in the case of a large R ₂, the distributed decoupling capacitor network degenerates into a system with a single capacitor. Capacitor C ₁ is therefore excessively large. Conversely, if C ₂ is placed close to C ₁ (R ₂ is small), C ₂ is excessively large and the system again behaves as a single capacitor. An optimal ratio $\frac{R_{2}} {R_{1}}$ therefore exists for specific characteristics of the current load that results in a minimum required on-chip decoupling capacitance. Alternatively, in this case, both capacitors provide an equal portion of the total charge (see Table 13.3 for R ₁ = 0. 5 Ω and R ₂ = 10 Ω). Also note that as the magnitude of the current load increases, larger on-chip decoupling capacitors are required to provide the expected current demands.

The parameters of a distributed on-chip decoupling capacitor network listed in Table 13.3 have been determined for the case where the magnitude of the decoupling capacitors is not limited. In most practical systems, however, the magnitude of the on-chip decoupling capacitor placed closest to the current load is limited by technology and design constraints. A case study of a system of distributed on-chip decoupling capacitors with a limited value of C ₁ is listed in Table 13.4. Note that in contrast to Table 13.3, where both R ₁ and R ₂ are design parameters, in the system with a limit on C ₁, R ₂ and C ₂ are determined by R ₁. Alternatively, both the magnitude and location of the second capacitor are determined from the magnitude and location of the first capacitor.

Table 13.4 The magnitude of the on-chip decoupling capacitors as a function of the parasitic resistance of the power/ground lines connecting the capacitors to the current load for a limit on C ₁

The parameters of the distributed on-chip decoupling capacitor network listed in Table 13.4 are determined for two amplitudes of the current load with R ₁ representing a typical parasitic resistance of the metal line connecting C ₁ to the current load. The resulting power supply noise at the current load and across the last decoupling stage is estimated using SPICE and compared to the maximum tolerable levels, respectively, V _load ^min and $V _{C_{2}}^{\mathrm{min}}$. Note that the analytic solution accurately estimates the parameters of the distributed on-chip decoupling capacitor network, producing a worst case error of 0.0001 %.

Comparing results from Table 13.4 for two different magnitudes of C ₁, note that a larger C ₁ results in a smaller C ₂. A larger C ₁ also relaxes the constraints for the second decoupling stage, permitting C ₂ to be placed farther from C ₁. The first stage of a system of distributed on-chip decoupling capacitors should therefore be carefully designed to provide a balanced distributed decoupling capacitor network with a minimum total required capacitance, as discussed in Sect. 13.4.3.

On-chip decoupling capacitors have traditionally been allocated during a post-layout iteration (after the initial allocation of the standard cells). The on-chip decoupling capacitors are typically inserted into the available white space. If significant area is required for an on-chip decoupling capacitor, the circuit blocks are iteratively rearranged until the timing and signal integrity constraints are satisfied. Traditional strategies for placing on-chip decoupling capacitors therefore result in increased time to market, design effort, and cost.

The methodology for placing on-chip decoupling capacitors presented in this chapter permits simultaneous allocation of the on-chip decoupling capacitors and the circuit blocks. In this methodology, a current profile of a specific circuit block is initially estimated [298]. The magnitude and location of the distributed on-chip decoupling capacitors are determined based on expected current demands and technology constraints, such as the maximum capacitance density and parasitic resistance of the metal lines connecting the decoupling capacitors to the current load. Note that the magnitude of the decoupling capacitor closest to the current load should be determined for each circuit block, resulting in a balanced system and the minimum required total on-chip decoupling capacitance. As the number of decoupling capacitors increases, the parameters of a distributed on-chip decoupling capacitor network are relaxed, permitting the decoupling capacitors to be placed farther from the optimal location (permitting the parasitic resistance of the metal lines connecting the decoupling capacitors to vary over a larger range). In this way, the maximum effective radii of a distant on-chip decoupling capacitor is significantly increased [277]. A tradeoff therefore exists between the magnitude and location of the on-chip decoupling capacitors comprising the distributed decoupling capacitor network.

7 Summary

A design methodology for placing distributed on-chip decoupling capacitors in nanoscale ICs can be summarized as follows.

• On-chip decoupling capacitors have traditionally been allocated into the available white space using an unsystematic approach. In this way, the on-chip decoupling capacitors are often placed far from the current load

• Existing allocation strategies result in increased power noise, compromising the signal integrity of an entire system

• Increasing the size of the on-chip decoupling capacitors allocated with conventional techniques does not enhance power delivery

• An on-chip decoupling capacitor should be placed physically close to the current load to be effective

• Since the area occupied by the on-chip decoupling capacitor is directly proportional to the magnitude of the capacitor, the minimum impedance between the on-chip decoupling capacitor and the current load is fundamentally affected by the magnitude of the capacitor

• A system of distributed on-chip decoupling capacitors has been described in this chapter to resolve this dilemma. A distributed on-chip decoupling capacitor network is an efficient solution for providing sufficient on-chip decoupling capacitance while satisfying existing technology constraints

• An optimal ratio of the parasitic resistance of the metal lines connecting the capacitors exists, permitting the total budgeted on-chip decoupling capacitance to be significantly reduced

• Simulation results for typical values of the on-chip parasitic resistances are also presented, demonstrating high accuracy of the analytic solution. In the worst case, the maximum error is 0.003 % as compared to SPICE

• A distributed on-chip decoupling capacitor network permits the on-chip decoupling capacitors and the circuit blocks to be simultaneously placed within a single design step