Short-Circuit Operation of a 650-V/60-A GaN-Based Half-Bridge

Abstract

The Short-Circuit (SC) robustness of GaN HEMTs represents a relevant issue for their use in power electronics. The research only focused on type I SC behavior of the single GaN transistor, in addition using large gate resistors during experimental tests. Here, we investigate the real case of a GaN-based Half-Bridge operating in SC conditions, focusing on the impact that another identical device can have on the SC. After designing and realizing a prototype test board with two 650-V/60-A GaN HEMTs, experimental SC tests confirm the theoretical analysis and highlight the effects of the DC-link voltage, demonstrating that both the presence of a second device and the use of large gate resistor can strongly alter the expected SC behavior.

1 Introduction

Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) can lead to high-frequency operation of power converters, ensuring at the same time high power density and efficiency [1]. However, considering the 650-V voltage rating, GaN HEMTs still present some limitations, such as the low Short-Circuit (SC) ruggedness [2].

In recent years, many studies and findings were conducted on the SC behavior of GaN devices: from the capability, degradation and withstand time tests [2,3,4,–[5], to instability [6, 7], failure mechanisms analysis [8], measurement techniques [9] and modelling aspects [10].

The SC characterizations presented in the literature are often carried out focusing on the single device, performing a SC directly on the DC-link capacitors or with another protection device with much higher current rating. However, these test conditions do not reflect the real case in practical applications, where the problem of the SC event can occur in converters based on Half Bridge (HB) configuration. Even the presence of the protection device placed in series to the GaN HEMT under test is far from the real SC event, because it always works in its linear region and never undergoes an electro-thermal stress [10, 11]. On the contrary, in the practical case the power devices of the bridge are equal and therefore the SC involves two identical devices, whose behavior should be analyzed. Moreover, very large values of turn-on gate resistance are often used to perform the SC tests, both to slow down the switching transients and to prevent instabilities. In fact, in [4] the authors use a 38 Ω gate resistor, while a 50 Ω resistor is used in [5]. In [3] 46–, 100–, 460-Ω values are used. In [2] the value is not provided, but it can be obtained from the experimental data of the gate current and voltage and it is about 60 Ω.

In this work, we study the SC operation of a HB with 650-V/60-A p-doped gate GaN HEMTs [12]. After a theoretical analysis, illustrated in Sect. 2, we performed experimental SC tests using a designed prototype in Sect. 3, evaluating the impact of DC-link voltage (${V}_{dc}$), gate resistor (${R}_{g}$) and the mismatch in the circuit loops of the two devices. Finally, Sect. 4 provides the conclusions of the work.

2 Theoretical Operation

The circuit scheme of Fig. 1(a) can be considered to study the SC operation of a HB, where ${V}_{s}$ represents a real DC voltage source with its impedance ${Z}_{s}$, ${C}_{DC}$ is the main DC-link capacitance, ${C}_{dc}$ is the decoupling capacitance, ${L}_{stray}$ represents the stray inductance between the main DC-link and ${C}_{dc}$ and ${Q}_{1}$, ${Q}_{2}$ are two identical GaN HEMTs. In first approximation, all the power loop parasitic inductance is lumped in ${L}_{p}$. To create the SC on the HB, the gates of ${Q}_{1}$ and ${Q}_{2}$ are driven by the logic signals shown in Fig. 1(b).

Fig. 1.

Basic circuit scheme of HB with GaN HEMTs (a) and driving signals (b) for the study of the SC behavior.

In phase II ${Q}_{1}$ is turned on and all ${V}_{dc}$ is applied at the drain of ${Q}_{2}$. In phase III ${Q}_{2}$ is also turned on while ${Q}_{1}$ is already on and the HB operates in SC conditions for the time duration ${T}_{SC}$. This situation, in which Q2 suffers from a type I SC and Q1 from a type II one, is certainly of applicative interest. In fact, it often occurs during debugging of a converter when it is possible that the control circuit commands by mistake the turning on of the two switches at the same time or when one of the two switches should be off and turns on due to noise on its gate while the other is on.

The SC current ${I}_{SC}$ is determined by the operating point on the output characteristic of device ${Q}_{2}$, visible in Fig. 2(a) for increasing junction temperatures (${T}_{j}$). ${Q}_{2}$ works in the saturation region and behaves like a controlled current source while it is still blocking almost all ${V}_{dc}$, suffering from a high instantaneous power dissipation that causes the increase of ${T}_{j}$. Instead, the operating point of ${Q}_{1}$, assuming that its ${T}_{j}$ is always lower than the one of ${Q}_{2}$, is located in the linear region of its output characteristic, and therefore it behaves like a current-controlled resistance defined by its ${R}_{DS,on}$, as graphically shown in Fig. 2(a). Hence, during the SC event the behavior of the two HEMTs is not the same and the electro-thermal stresses are also different. In the described condition, ${Q}_{2}$ can be considered the device which leads the SC current, as it works in the saturation region, and ${Q}_{1}$ “follows” the current by varying its voltage drop acting as a variable resistor. Consequently, the equivalent scheme of the HB during the SC event is the one shown in Fig. 2(b), with a controlled current source and the on-resistance of the other device. In general, all the SC stress is borne by the device which turns on after its blocking phase: in fact, the same reasoning could be conducted swapping the driving signals of the two devices, turning on ${Q}_{2}$ first and ${Q}_{1}$ afterwards. In this case, the roles of the switches would be inverted, with ${Q}_{1}$ operating in the saturation region and bearing all the SC stress.

Fig. 2.

Operating points of Q1 and Q2 on the drain I–V plane (a) and equivalent scheme of the Half-Bridge (b) during SC.

2.1 Simulation Analysis

The effect of various circuit parameters, including ${V}_{dc}$, the gate driver voltage and the SC pulse width ${T}_{SC}$, has been already investigated in many works [2, 4, 5]. No unexpected behaviors can be observed when evaluating the SC operation of the HB instead of the single device. The peak SC current is directly dependent on the gate voltage, while it undergoes a higher reduction as ${V}_{dc}$ increases, while a larger ${T}_{SC}$ is related to a higher dissipated SC energy, that can bring the device to the failure [2].

However, when a mismatch in the common-source inductance (${L}_{s}$) of the devices is present in the circuit, the behavior of the two GaN HEMTs can be swapped and ${Q}_{1}$ can work in saturation region, even if it is turned on before ${Q}_{2}$ and should work in linear region. As a demonstration, a LTSpice simulation was conducted considering the circuit in Fig. 3, that includes the main parasitic elements in the gate and power loops of the HB. The parameters used for the simulation are listed in Table 1, while ${V}_{dc}$. Was varied from 100 V to 400 V. The LTSpice model supplied by the manufacture was used for the GS66516T GaN HEMT [12]. With ${L}_{s1}$ on the gate loop of ${Q}_{1}$ 20% higher than ${L}_{s2}$, the behavior of the two HEMTs can be swapped, as visible from the SC loci of Fig. 4, derived from the simulated drain current and voltage of the two transistors. When ${V}_{DS,1}$, that starts from 0 V, becomes higher than ${V}_{DS,2}$, that starts from ${V}_{dc}$, the behaviors of the two GaN HEMTs are swapped and ${V}_{DS,1}$ tends to ${V}_{dc}$ while ${V}_{DS,2}$ goes to its on-state voltage. This happens when ${V}_{dc}$ is lower than 300 V in the simulated test conditions. In this case, the power dissipation of ${Q}_{1}$ is higher than in ${Q}_{2}$, since it is subjected to high ${V}_{DS}$. When ${V}_{dc}$ is higher than 300 V ${V}_{DS,1}$ and ${V}_{DS,2}$, even showing a transient increase and decrease respectively, do not overlap anymore and ${V}_{DS,1}$ tends to its on-state voltage drop, while ${V}_{DS,2}$ tends to ${V}_{dc}$.

Table 1. Parameters used in LTSpice simulation.

Fig. 3.

Circuit simulated in LTSpice.

Fig. 4.

SC loci of the two GaN HEMTs in the presence of mismatch in common-source inductance, with Ls1>Ls2.

Hence, for ${V}_{dc}$ < 300 V, ${Q}_{1}$ works in saturation and ${Q}_{2}$ in the linear region, even if ${Q}_{2}$ turns on after its blocking phase. This can be explained considering the output characteristics and the drain voltage and temperature waveforms. After the transient turn-on phase of device ${Q}_{2}$, the steady-state equilibrium point is determined by the intersection of the output characteristics of the transistors. The difference in the stray inductances on the source path is responsible for the transient variation of ${V}_{DS,2}$, that becomes lower than ${V}_{DS,1}$ for ${V}_{dc}<$ 300 V, as highlighted in Fig. 5(a).

These facts lead ${Q}_{1}$ to dissipate more power than ${Q}_{2}$, increasing its junction temperature ${T}_{j,1}$, that becomes higher than ${T}_{j,2}$ of ${Q}_{2}$, as shown in Fig. 5(b). Since ${T}_{j,1}>{T}_{j,2}$, the output characteristic of ${Q}_{1}$ intersects the one of ${Q}_{2}$ in the linear region of this latter one, leading ${Q}_{1}$ to operate in the saturation region and ${Q}_{2}$ to work in the linear region at the steady state. For ${V}_{dc}$ higher than 300 V, whose waveforms are not reported here for brevity, the opposite situation is established, as ${Q}_{1}$ shows a lower drain voltage at the beginning of the SC and, even if it goes in the saturation region during the transient, ${V}_{DS,2}$ of ${Q}_{2}$ is always higher, leading to a higher power dissipation and temperature increase. So, in the steady state it works in the saturation region, while ${Q}_{1}$ works in the linear region.

Fig. 5.

Simulated waveforms at V_dc = 100 V: V_DS (a) and T_j (b) of the two GaN HEMTs.

3 Experimental Short-Circuit Tests

The experimental SC tests were conducted on a designed prototype at different ${V}_{dc}$, from 50 V to 400 V, using two values for ${R}_{g}$, namely 100 Ω and 22 Ω. These values for ${R}_{g}$ were selected to show the possible impact that the proper choice of ${R}_{g}$ can have in practical applications. In fact, as stated before, in most of experimental SC characterizations presented in the literature large gate resistors are used (cf. 1). This condition has no impact on the type I SC of the single device, but it may affect the SC behavior of the HB, and for this reason two very different values of gate resistance are used here. In fact, the 22 Ω resistor is practically used when working with GaN HEMTs in normal operations at high frequency, at the opposite of the 100 Ω resistor which is never used in a real converter.

The SC pulse-width was set to 5 μs and the gate drivers voltage levels are +5 V and 0 V for on and off states, respectively. This choice ensures the full turn-off of the device, that has a typical threshold voltage of 1.6 V.

The SC waveform with ${R}_{g}$ = 100 Ω are depicted in Fig. 6, showing the drain current ${I}_{D}$ (corresponding to ${I}_{SC}$, equal for the two devices) and ${V}_{DS}$ of both GaN HEMTs. It must be clarified that the drain-source voltage of ${Q}_{1}$ (${V}_{DS1})$ was not directly measured during the tests, but it was obtained from the voltage balance in the output loop, referring to Fig. 1, as ${V}_{dc}-{V}_{DS2}-{L}_{p}d{I}_{D}/dt$. The contribution of ${L}_{p}$ was numerically included during the computation of ${V}_{DS1}$ and although this fact causes some numerical errors when evaluating ${V}_{DS1}$, especially at the turn-on and turn-off transients, the waveforms of ${V}_{DS1}$ during the SC event are reliable and can be used to evaluate the SC behavior of the device.

The drain current waveforms show the typical behavior during the SC, reaching a peak value in about 900 ns and then decreasing to lower values because of the increase of ${T}_{j}$. In particular, ${I}_{D}$ reaches a peak of 173 A and then decreases to about 125 A at ${V}_{dc}=$ 50 V (see Fig. 6(a)). As ${V}_{dc}$ increases, the peak of the SC current slightly decreases to about 166 A, while its final value undergoes a huge drop, that becomes larger with increasing ${V}_{dc}$. At ${V}_{dc}=$ 400 V the peak SC current is about 160 A and it is reduced by 70% after 2 μs, becoming equal to about 50 A. At the end of the SC, the final value is 35 A, indicating that the current decreased by 80% with respect the initial value (see Fig. 6(a)).

Fig. 6.

Waveforms during SC tests at different V_dc and R_g = 100 Ω: drain current (a) and drain voltage of Q₁ (b) and Q₂ (c).

The drain voltage waveforms are indicative of the roles played by the two devices during the SC event. Almost all ${V}_{dc}$ is applied to ${Q}_{2}$, that works in the saturation region for all the SC duration. On the contrary, ${Q}_{1}$ starts from 0 V and in 1 μs reaches a peak value, that increases with ${V}_{dc}$ but remains between 11.5 V and 16.0 V. After that, its value decreases to less than 5 V and at ${V}_{dc}=$ 400 V it goes to about 0.3 V (see Fig. 6(b)). In correspondence of the peak value of ${V}_{DS1}$, ${V}_{DS2}$ experiences the largest voltage drop, reaching 380 V and 38 V in the extreme cases of ${V}_{dc}=$ 400 V and ${V}_{dc}=$ 50 V, respectively (see Fig. 6(c)). Therefore, the behavior of the two devices complies with the theoretical analysis introduced in Sect. 2. In fact, ${Q}_{2}$ works in the saturation region and ${Q}_{1}$, after a transient working point in the saturation region operates in its linear region.

The common-source inductance measured on the real prototype is 0.8 nH for ${Q}_{1}$ and 0.4 nH for ${Q}_{2}$. However, even if a mismatch in the common-source inductance in the two gate loops is present, no effect is visible in the waveforms, meaning that the large ${R}_{g}$ helps in reducing the effect of ${L}_{s}$ on the two devices.

The waveforms with ${R}_{g}$ = 22 Ω, derived from experimental SC tests conducted on new devices, are shown in Fig. 7. The drain current reaches a peak value of about 177 A at ${V}_{dc}=$ 50 V and then it slightly decreases, with the increase of ${V}_{dc}$, down to 170 A at 400 V. Instead, the ${I}_{D}$ value at the end of the SC reaches 133 A at ${V}_{dc}=$ 50 V and 43 A at ${V}_{dc}=$ 400 V, that represent a drop of the 25% and 75% with respect the peak value, respectively (see Fig. 7(a)). These final values of ${I}_{D}$ are quite higher than the final values in the previous case.

Fig. 7.

Waveforms during SC tests at different V_dc and R_g = 22 Ω: drain current (a) and drain voltage of Q₁ (b) and Q₂ (c).

In this condition the behaviors of ${Q}_{1}$ and ${Q}_{2}$ are swapped for ${V}_{dc}$ < 250 V, as visible from the ${V}_{DS}$ waveforms of Fig. 7(b) and Fig. 7(c). In fact, except for ${V}_{dc}=$ 100 V, ${Q}_{1}$ blocks a higher voltage than ${Q}_{2}$, even if, from a theoretical point of view, ${Q}_{2}$ should block a higher percentage of ${V}_{dc}$. At ${V}_{dc}=$ 50 V ${V}_{DS1}$ reaches 45 V and then decreases to 35 V, because ${V}_{dc}$ also decreases (see Fig. 7(b)), while ${V}_{DS2}$ remains at about 4.5 V (see Fig. 7(c)). This means that the roles of the two devices are swapped and ${Q}_{1}$ operates in the saturation region, while ${Q}_{2}$ is in its linear region. The behavior is inverted at ${V}_{dc}=$ 100 V, where ${Q}_{2}$ blocks almost all ${V}_{dc}$. However, at 150 V and 200 V, both ${Q}_{1}$ and ${Q}_{2}$ operate at high ${V}_{DS}$ for a long period of the SC event. In fact, at ${V}_{dc}=$ 200 V, ${V}_{DS1}$ shows a peak of 175 V, then it has a drop to 85 V and then increases again up to 163 V. ${V}_{DS2}$ shows the opposite behavior, with a drop from 200 V to 20 V at the beginning of the SC, a consequent increase up to 100 V and, then, a further reduction to 20 V at the end of the SC. For ${V}_{dc}$ higher than 200 V, the two devices return to operate as expected, with ${Q}_{2}$ blocking almost all ${V}_{dc}$ for a large part of the SC pulse-width. However, it is worth noting a strong voltage dip in ${V}_{DS2}$ at the beginning of the SC, caused by the high di/dt, that is responsible also for the transient increase of ${V}_{DS1}$.

To provide an overall indication about the SC, the energy (${E}_{SC}$) dissipated by both devices was computed between the start and final time instants of the SC, indicated with ${t}_{i}$ and ${t}_{f}$, respectively, starting from the experimental drain current and voltage, according to (1):

$${E}_{SC} = \int\nolimits_{{t}_{i}}^{{t}_{f}}{I}_{D}\left(t\right){V}_{DS}\left(t\right)\,dt$$

(1)

The SC energy for the two GaN HEMTs is plotted in Fig. 8(a) as a function of ${V}_{dc}$ for both cases ${R}_{g}=$ 100 Ω and ${R}_{g}=$ 22 Ω. As expected and clearly visible, the SC energy of ${Q}_{2}$ is much higher than ${Q}_{1}$ for ${R}_{g}=$ 100 Ω and for ${R}_{g}=$ 22 Ω for all ${V}_{dc}$ values higher than 250 V. The non-monotonic trend in the SC energy for ${R}_{g}=$ 22 Ω and ${V}_{dc}$ < 250 V, observed in the figure, is due to the different behavior of the two devices when ${V}_{dc}$ is lower than 250 V, as previously described.

A global comparison between the total SC energy, computed as the sum of ${Q}_{1}$ and ${Q}_{2}$ energies, for the two values of ${R}_{g}$ is shown in Fig. 8(b), where it can be noted that the total SC energy is higher for ${R}_{g}=$ 22 Ω in all ${V}_{dc}$ conditions, and the difference between the total energies becomes larger as ${V}_{dc}$ increases. This fact can be explained considering that the ${I}_{D}$ values in the case ${R}_{g}=$ 22 Ω were higher than the ones with ${R}_{g}=$ 100 Ω, leading to a higher mean power dissipation during the SC event.

Fig. 8.

SC energy of device Q₁ and Q₂ (a) and total SC energy (b) versus V_dc in comparison between R_g = 22 Ω and R_g = 100 Ω, in the condition V_G = 5 V.

4 Conclusion

The Short-Circuit analysis of GaN HEMTs should be performed in real operating conditions to obtain reliable and meaningful results. In this work the SC is performed on a Half-Bridge with 650-V/60-A GaN HEMTs, evaluating the impact that another device can have on the SC behavior of the transistor. The theoretical analysis showed that under ideal conditions the device that turns on after the blocking phase undergoes a type I SC, while the other one undergoes a type II SC. However, a mismatch in the common-source inductance in the loops of the two devices can swap the behavior of the two transistors, as highlighted by the simulations. The experimental results confirm the theoretical analysis and show the impact of the gate resistor in characterizing the SC robustness of GaN HEMTs. In fact, the use of large gate resistor, besides having low practical usefulness, leads to an underestimation of the SC energy and its electro-thermal stress, even if it eliminates the possible parasitic effects due to the common-source inductance. Therefore, an accurate SC analysis must be performed on a realistic configuration, as a HB, and with practical operating conditions to obtain consistent and reliable results.