Keywords

1 Introduction

The continuous advancements in integrated circuits (ICs) miniaturization have resulted in a significant increase in the density of Printed Circuit Boards (PCBs). These latter, on the other hand, in line with scientific and commercial demands, have progressively reduced in size while requiring the integration of a high number of interfaces and on-board computational capabilities [1,2,3,4]. In this context, the utilization of power-hungry electronic components prone to overheating, such as CPUs, GPUs, FPGAs, and voltage regulators, made the proper thermal design of PCBs crucial [1, 2]. This aspect, which was often underestimated, overlooked, or addressed retrospectively, is gaining paramount importance. The reasons behind this trend are manifold: (i) the presence of heat-sensitive devices; (ii) the increased risk of failure and reduced lifespan of components exposed to heat; (iii) the derating of power dissipation as junction temperatures rise; (iv) the decrease in electrical performance associated with die overheating [5, 6]. This aspect is also important, especially in applications that involve the use of heat-sensitive sensors located on the small PCB near to “hot” ICs (e.g., temperature, optical, pressure, and gas sensors) [7, 8]. The study of the thermal influence of power-hungry ICs on the surrounding components depends on the preferred heat transfer process: (i) heat conduction in solids, (ii) heat convection in fluids and gases, and (iii) heat generated by radiation. Specifically, in the context of thermal analysis of PCBs, the heat transfer process depends on the packages used for the ICs. Most of the currently employed packages favor conduction as a fundamental method of heat transfer. Miniaturization has led to the widespread use of packages called Quad-Flat-No-Lead (QFN) and similar [9, 10]. These packages offer the advantage of small footprints, excellent heat conduction properties from the die to the exposed pad (EP) located on the component's bottom, and good electrical signal integrity as the EP is typically connected to the ground. Nevertheless, since heat is transferred from the die to the PCB through the EP, accurate modeling of the thermal behavior of the board is necessary.

The current state of common practice relies on the utilization of two methods for thermal analysis of Quad Flat No-Lead (QFN) packages: Computational Fluid Dynamics (CFD) with conjugate heat transfer (CHT) analysis and the Finite Element Method (FEM). These methods have demonstrated high accuracies in predicting heat transfer mechanisms and, for this reason, they have been integrated into widely used scientific and commercial simulators (e.g., COMSOL, ANSYS, etc.) [11]. Besides the substantial cost associated with these tools, the simulators employ adaptive and iterative algorithms for the volumetric fragmentation (e.g., meshing) of the domain under analysis. This process proves to be extremely time-consuming even for coarse fragmentations, theoretically designed to be quicker. Consequently, incorporating a feedback step into the workflow concerning multi-layer PCB design or the design of cooling devices like heatsinks becomes challenging. In this context, a few state-of-the-art solutions have been proposed. OnSemi, in [2], has presented a solution for the rapid estimation of heat transfer in PCBs incorporating QFN packages by establishing an electrical equivalent of the thermal behavior of the board. Specifically, they designed a resistive network employing an approach named axisymmetric. This method is constrained to modeling the PCB region beneath the EP and employs a coordinate transformation from Cartesian to radial, assuming the copper planes into inner layers to be rectangular or square. Additionally, this method fails to achieve accurate estimations when the copper polygons, as frequently occurs, exhibit irregular profiles, disregarding the substantial lateral thermal resistance of the dielectric within the inner layers when interspersed with splits in the planes. Authors in [12] devised a solver that analyzes gerber files pixel-by-pixel, associating with each a system of fluid dynamics equations across six principal directions. The system demonstrated good accuracy when juxtaposed with CFD tools; nonetheless, given the substantial number of pixels composing a set of gerber files describing a multi-layer PCB, the computational burden becomes excessively high to implement a quick estimator.

In this context, the present paper introduces an automated tool for heat transfer estimation in a multi-layer PCB embedding QFNs. The primary strength of the design lies in its ability to generate a heatmap of the board within a few seconds (<10 s for up to 32 layers), allowing real-time feedback for appropriate placement of heat-sensitive components around power-hungry QFN ICs. This is made possible by an automated PCB feature extraction system based on an image processing algorithm applied to gerber files. This algorithm simplifies heat diffusion paths by considering the relative presence of metal and dielectric/solder mask in the analyzed areas, even in presence of irregular metal polygon shapes. Lastly, through analysis of the stack-up's CSV file, the system can derive a resistive network netlist that describes the thermal equivalent in the electrical domain. A SPICE simulation on the extracted resistive network is ultimately conducted, providing a steady-state thermal measurement.

2 The Proposed System

Figure 1 illustrates the detailed workflow of the proposed tool, which consists of four main phases: Initialization, Thermal Path Analysis, Resistive Network Modeling, and SPICE Simulation.

Fig. 1.
figure 1

Overall workflow of the proposed tool

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2.1 Phase 1: Initialization

During the initialization phase, the user must load, via a dedicated Graphical User Interface (GUI), the: (i) gerber files with.JPG extension or Altium standard extensions; and (ii) the stack-up file in.CSV format.

An illustration of gerber files (two out of four layers) and a stack-up table for a sample PCB is shown in Fig. 2. During this phase, the layer and interposed dielectric thicknesses are extracted from the stack-up file. From the individual gerber files, photosensitive masks are determined, indicating the areas where metal will be present. In this context, during initialization, the user is prompted to define the metal (e.g., Copper [Cu]) and the dielectric (e.g., FR4) to be modeled. As can be noticed from Fig. 2, there are two types of layers in the stack-up file: signal and plane layers. A signal layer is realized through a positive mask, where colored areas correspond to metallic zones. Plane layers are negative masks, where white areas correspond to metal regions. Once materials are defined and the plane layers are converted into positive masks, the GUI enables the user, via a point-and-click system, to select the Device Under Test (DUT) through the assembly layer. This selection serves the purpose of automatically defining the EP area.

Fig. 2.
figure 2

Overview of gerbers (2 out of 4 layers) and stack-up files to be uploaded in the automatic tool. For the sake of example, the Gerber files section distinguishes between Signal and Plane layers.

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Currently, tool permits to select only QFN ICs for the analysis; however, the generality of the here presented method will allow easy integration of various IC package families.

2.2 Phase 2: Thermal Path Analysis

During the Thermal Path Analysis phase, the tool initially partitions the test area (defined by the user through a point-and-click system) into two types of elements, namely IC Elements and Radial Elements. The first element (i.e., IC Element) is derived from the QFN's landing pattern. It encompasses the entire volume beneath an octagonal area inscribing the QFN's EP. Figure 3 depicts an example of an IC Element area (on an outer layer) obtained from the landing pattern. The octagon is further subdivided into eight sub-elements of triangular shape, one for each simplified propagation direction. From each of these eight propagation directions, a cascade of Radial Elements is realized, as schematized in Fig. 3.

Once the elements are defined (Test Area Fragmentation), the process moves on to defining their physical composition. This phase, referred to as Element Composition in Fig. 1, aims to analyze the percentage of metal and dielectric (inner layers) or solder mask (outer layers) along the propagation direction within the analyzed element. For this purpose, the image processing algorithm implemented by the tool extracts all elements as subsets of pixels [13]. Subsequently, within each element, three possible areas are identified along the propagation direction, denoted as \(n_{px1..3}\). The interval \(n_{px1}\) represents the number of pixels from the origin of the frame, defined by the propagation source (e.g., first column on the left in Fig. 3), to the first pixel belonging to the metal mask. If the frame starts with at least one pixel of the metal mask, \(n_{px1}\) = 0. The interval \(n_{px2}\) corresponds to the number of pixels within the area ranging from the column containing the first pixel of the metal mask to the column containing the last “metallic” pixel. Finally, like \(n_{px1}\), \(n_{px3}\) represents the number of pixels within the interval between the column containing the last pixel of the metal mask and the last column of the analyzed frame. \(n_{px3}\) = 0 if the last column contains pixel from metal mask. The number of pixels belonging to the metal mask divided by the total number of pixels in the \(n_{px2}\) area determines the percentage used to subsequently extract the equivalent resistive model. The complementary value represents the percentage of dielectric or solder mask. Irregular-profile masks are, thus, simplified as shown in Fig. 3 as a combination of rectangles. This simplification offers the advantage of reducing computational complexity by avoiding the analysis of conduction effects on individual pixels while preserving information concerning the thermal path along metallic areas (low thermal resistivity) or regions with high thermal resistivity (e.g., dielectric) that impede heat flow.

Fig. 3.
figure 3

Demonstrative schematization of Test Area Fragmentation and Element Composition Phases. The figure reports the equivalent resistive network for coplanar heat transfer process.

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2.3 Phase 3: Resistive Network Modelling

Once the representation of the PCB layers has been simplified by redefining the elements as depicted in Fig. 3, the tool proceeds to extract the resistive network for the thermal equivalent. Figure 3 illustrates the equivalent coplanar circuit (layer containing metal) for an ith layer belonging to both the IC Elements and Radial Elements stacks. The resistive network is derived using a combination of formulas for extracting the thermal resistance of a parallelepiped:

$$\theta = \left( {\frac{1}{{\lambda_{mat} }} \cdot l} \right)/A$$
(1)

where \(\lambda_{mat}\) is the thermal conductivity of the analyzed material (e.g., Cu, Soldermask, FR4); \(l\) is the length along the x-axis of the metal or dielectric parallelepipeds in coplanar resistances and the thickness of the dielectric in the vertical modeling of the board (Fig. 4); \(A\) equals the cross-sectional area of the parallelepiped along the direction of analysis of the resistor, in accordance with Ohm's law.

It is necessary to specify that once the coplanar sections are extracted, the system also generates the model for the equivalent vertical thermal resistance, considering the dielectric interposed between the layers. The model and an example stack are shown in Fig. 4. Particular attention is devoted to the vertical modeling of the IC Elements section. In this case, the presence of a certain number of thermal vias in the EP is accounted for by inserting the thermal resistance related to the N thermal vias in parallel with \(\theta_{FR4_h }^{L_{i \to i + 1} }\). This thermal resistance will be extremely low, predominating in the parallel configuration. Consistent with existing literature [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17], this is indeed considered the preferred heat transfer path in QFN packages.

Further details regarding the formulas employed for modeling the resistive network can be found in the previous work [14].

Fig. 4.
figure 4

Vertical Modelling of PCB elements focused on two subsequent layers Li and Li+1

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2.4 Phase 4: SPICE Simulation

Once the resistive model describing the PCB has been finalized, the user is prompted to input three parameters, which are obtainable from the IC's datasheet: (i) the junction-board or die-EP thermal resistance, \(\theta_{J - EP}\) (the solder paste thermal resistance can be added for more precise estimation); (ii) the thermal resistance between the junction and the top of the case, \(\theta_{J - T}\) (typically 20–50 ℃/W for plastic mold, default 40 ℃/W); (iii) the parameter h or heat transfer coefficient (sometimes film coefficient) for determining the \(\theta_{ex}\) for heat exchange interface between a body and the surrounding air. Additionally, it is possible to request the insertion of a heatsink thermal resistance, \(\theta_{Heatsink}\), if the preliminary study of its effect is desired.

Once all the necessary parameters are provided, the tool will automatically generate a netlist file with a. cir extension. This netlist file will report the equivalent thermal resistance of the PCB as a passive network, \(\theta_{tool - PCB}\), , the previously defined ambient thermal resistances as the electric counterpart, the power to be dissipated (PD) represented as a DC current generator, and the ambient temperature (TA) through a DC voltage generator. The netlist will include a bias point simulation, corresponding to a steady-state thermal analysis. Currently, the extracted.cir file has been tested with Pspice A/D integrated in OrCAD 17.4. Optionally, the system allows for conducting parametric simulations for the design of cooling devices based on the power to be dissipated, PD, or to define the range of dissipable power based on commercial heatsink thermal resistances, \(\theta_{Heatsink} .\)

Figure 5.a presents a simplified version of the implemented equivalent circuit, while Fig. 5.b provides an example of a netlist and the output file of the bias point analysis.

3 Experimental Results

To provide an overview of the accuracy and speed performance of the here-proposed estimator, the system has been validated through comparison with a professional heat transfer analysis tool (i.e., Ansys 2023 r1).

3.1 Sample PCB Characteristics

The sample board used for comparison is the power supply module of a more general PCB used in railway applications [2, 15]. This power supply module integrates a Power Management IC with QFN package capable of providing 4 switching and a linear output channel, overall dissipating 1W in the worst-case. The QFN’s EP size is 5.6 mm × 5.6 mm, which determines the extraction pitch of the Radial Elements for modelling. The test board has the following dimensions: 51 mm × 44 mm, thickness 1.43 mm. The PCB has 10 layers of which 2 (connected to ground) are dedicated to dissipation. The thickness of all layers of the board is ½ oz (~18 μm, 35μ m with finishing on outer layer). The IC is placed on the top (L1) of the test board.

Fig. 5.
figure 5

SPICE Simulation. (a) Simplified equivalent electrical circuit; (b) Netlist and bias point output demonstrative snapshots.

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3.2 Estimation Tool Performance

The validation of the proposed tool has been carried out by considering six points for the calculation of the radial elements located along each of the four main axes, identified in Fig. 6 as the x-axis, y-axis, diag-1, and diag-2 (red points - Fig. 6). The points have been set equidistantly with a step size of d = 5.6 mm (EP side length). The central point, at a distance of 0 mm from the junction, corresponds to the evaluation coordinates of the IC Element (yellow point - Fig. 6). A total of 25 points per layer have been extracted (250 points for 10 layers).

In the Ansys environment, each assessment point has been instrumented with temperature probes, and a Steady-State Thermal analysis has been performed using convection parameters and material selections in line with what was defined for the developed estimator. For the calculation, an adaptive mesh was generated with automatic shaping and manually optimized element sizing to minimize the skewness parameter.

Figure 6 presents on the left a graphical representation of the analyzed points, with an isometric view of the top layer (L1). On the right side of Fig. 6, the upper subplot displays the mean of the absolute value of the difference between the measurements conducted using Ansys (FEMT) and the estimations generated by the proposed tool (ModelT), as a function of the distance from the junction. The graph includes error bars with the upper limit indicating the maximum error incurred and the lower limit representing the minimum mismatch between the measurements.

Fig. 6.
figure 6

Sample PCB analysis. Isometric top view of sample board to identify assessment points location. Upper subplot: Comparison between Ansys-based measurements and tool-based ones along x and y axes, diag-1 and diag-2. Bottom subplots: error graphs along main directions.

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The four lower subplots are instead dedicated to specific errors along each single direction.

Overall, the simulation results in Fig. 6 showed that the estimator exhibits an average error <1 ℃ within an area of 7.1 cm2 and <3 ℃ within an area of 12.5 cm2 considering the layer 1 (L1 (top)). The results improve on the widely and uniformly distributed ground layers (L2 and L9), where the estimation error remains below 2 ℃ for an area of 24.63 cm2. Presumably, this is due to the greater uniformity of the copper polygon that cover the whole PCB area with a few splits mainly due to vias. It is in contrast to the outer layers that are significantly irregular and heterogeneous due to traces and components.

To assess the computation timing, the thermal analyses with Ansys software and the developed estimator have been conducted on a PC with an Intel Xeon® E-2104G processor - 3.20 GHz, and 32 GB of RAM. The Ansys analysis needed 494.88 ms for the PCB sample meshing and 271.81 s for the temperature analysis, totaling 766.69 s. The analysis using the estimator necessitated 5.25 s for the resistive network modelling and 3.16 s for the bias point calculation with the SPICE simulator, resulting in a total of 8.41 s (91.16 times faster).

4 Conclusions

A real-time automated tool for modeling heat transfer in a PCB with QFNs has been presented. This tool employs a novel approach to define and employ resistive networks to depict PCB heat flow. Notably, it adapts to irregular copper layer shapes, critical limitation for most of quick estimators at the state of the art but really common in PCB design. The tool autonomously extracts data from Gerber and stack-up files, including copper-dielectric ratios and thermal connections. It offers crucial support for designers by aiding components placement to enhance sensing accuracy and heat-sensitive components lifespan. Tested on a 10-layer sample PCB, the model yielded precise temperature predictions, with <3 ℃ deviations compared to Ansys in an area of 12.5 cm2 around the IC, but drastically reducing simulation time (~90 times). The achieved results are promising from the perspective of developing pseudo real-time analysis tools for the thermal behavior of electronic boards. Prospectively, it can provide feedback during the design phase, thereby preventing errors in heat-sensitive components placements and incorrect design choices (e.g., layer thicknesses, plane splits, etc.), improving electronic devices lifespan.