Abstract
Due to the limitations of CMOS technology, such as hard lithography, power consumption, and sub threshold effects, the researchers sought an alternative method. The unique properties of QCA technology, including as speed, low power dissipation, and small component size, motivated this research to investigate it as a CMOS alternative. This paper proposes a unique layout for a three-input single-layer majority gate. The proposed majority gate is used to create a revolutionary low-power RAM cell. Designing a low-cost memory cell would be a major difficulty since it is a component of the overall RAM, which is considered as the most important part of a digital gadget. The proposed RAM cell considerably decreases switching energy. The QCA Designer tool was used in this work for circuit design and execution, whereas the QCA Pro programme was used for power analysis.
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Babu, J.C., Suresh, Y., Rani, R.S., Yasmeen, S., Reddy, K.S.R.K., Harshavardhan, K. (2024). Accelerated Addition in Resistive Ram Array Using Parallel-Friendly Majority Gates. In: Gunjan, V.K., Zurada, J.M., Singh, N. (eds) Modern Approaches in Machine Learning and Cognitive Science: A Walkthrough. Studies in Computational Intelligence, vol 1117. Springer, Cham. https://doi.org/10.1007/978-3-031-43009-1_10
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