Abstract
Algorithms and tools for XML-documents processing are reviewed. The document analyzer algorithms, which are implemented in the stack state machine, are considered. A need for high-speed reconfigurable hardwired XML-request analyzers is determined. The SM16 processor architecture core is developed which effectively evaluates the stack-based parsing algorithms and is implemented in the field-programmable gate array (FPGA). The processor has the stack architecture with three additional stack blocks, hash-table, and instructions that accelerate the execution of parsing operations. The hardware/software FPGA-based system, which has the main processor and tens to hundreds of SM16 executive processor elements, is proposed. This system is scalable for different amounts of packets streams. It efficiently processes XML-documents and can be easily reconfigured to the given document grammars, allowing to adapt to fast-changing modern-world communications.
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References
Head, M.R., Govindaraju, M., van Engelen, R., Zhang, W.: Benchmarking XML processors for applications in grid web services. In: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing (2006)
Driscoll, D., Mensch, A.: Devices profile for web services ver. 1.1 (2009). http://docs.oasis-open.org/ws-dd/dpws/wsdd-dpws-1.1-spec.html
Schneider, J., Kamiya, T.: Efficient XML Interchange (EXI) Format 1.0 (2011). http://www.w3.org/TR/exi/. Accessed 9 Nov 2019
Apparao, P., Bhat, M.: A detailed look at the characteristics of XML parsing. In: BEACON-1: 1st Workshop on Building Block Engine Architectures for Computers and Networks (2004)
Mattias, N., Jasmi, J.: XML parsing: a threat to database performance. In: Proceedings of the 20th International Conference on Information and Knowledge Management CIKM 2003, pp. 175–178 (2003)
SAX Parsing Model. http://sax.sourceforge.net. Accessed 11 Nov 2019
Document object model (DOM) level 2 core specification. http://www.w3.org/TR/DOM-Level-2-Core. Accessed 11 Nov 2019
Murata, M., Lee, D., Mani, M., Kawaguchi, K.: Taxonomy of XML schema languages using formal language theory. ACM Trans. Internet Technol. 5(4), 660–704 (2005)
XML Path Language Version 1.0. http://www.w3.org/TR/xpath. Accessed 11 Nov 2019
Chiu, K., Devadithya, T., Lu, W., Slominski, A.: A binary XML for scientific applications. In: Proceedings of the IEEE 1st International Conference on e-Science and Grid Computing (e-Science 2005), pp. 336–343. IEEE (2005)
Lu, W., Chiu, K., Pan, Y.: A parallel approach to XML parsing. In: Proceedings of the 7th IEEE/ACM International Conference on Grid Computing, pp. 223–230. IEEE/ACM (2006)
Head, M.R., Govindaraju, M.: Approaching a parallelized XML parser optimized for multi-core processor. In: Proceedings of the 2007 Workshop on Service-Oriented Computing Performance: Aspects Issues and Approaches (SOCP 2007), pp. 17–22 (2007)
Altinel, M., Franklin, M.J.: Efficient filtering of XML documents for selective dissemination of information. In: Proceedings of the 26th International Conference on Very Large Data Bases (VLDB 2000), pp. 53–64 (2000)
Diao, Y., Altinel, M., Franklin, M.J., Zhang, H., Fischer, P.: Path sharing and predicate evaluation for high-performance XML filtering. ACM Trans. Database Syst. (TODS) 28, 467–516 (2003)
Green, T.J., Gupta, A., Miklau, G., Onizuka, M., Suciu, D.: Processing XML streams with deterministic automata and stream indexes. ACM Trans. Database Syst. (TODS) 29, 752–788 (2004)
Silvasti, P.: XML-document-filtering automaton. In: Proceedings of the Very Large Data Base Endowment (VLDB Endowment 2008), vol. 1, no 2, pp. 1666–1671 (2008)
Lunteren, J.V., Engbersen, T., Bostian, J., Carey, B., Larsson, C.: XML accelerator engine. In: 1st International Workshop on High Performance XML Processing (2004)
El-Hassan, F., Ionescu, D.: SCBXP: an efficient hardware-based XML parsing technique. In: 5th Southern Conference on Programmable Logic (SPL), pp. 45–50. IEEE (2009)
Mueller, R., Teubner, J., Alonso, G.: Streams on wires—a query compiler for FPGAs. In: Proceedings of the Very Large Data Base Endowment (VLDB Endowment 2009), vol. 1, no. 2, pp. 229–240 (2009)
Moussalli, R., Salloum, M., Najjar, W., Tsotras, V.: Massively parallel XML twig filtering using dynamic programming on FPGAs. In: Proceedings of the IEEE 27th International Conference on Data Engineering (ICDE 2011), pp. 948–959. IEEE (2011)
Mitra, A., Vieira, M., Bakalov, P., Najjar, W., Tsotras, V.: Boosting XML filtering with a scalable FPGA-based architecture. In: Proceedings of the CIDR 2009 - 4th Biennal Conference on Innovative Data Systems Research (2009)
Teubner, J., Woods, L., Nie, C.: XLynx—an FPGA-based XML filter for hybrid XQuery processing. ACM Trans. Database Syst. (TODS) 38(4), 1–39 (2013)
Woods, L., Alonso, G., Teubner, J.: Parallelizing data processing on FPGAs with shifter lists. ACM Trans. Reconfigurable Technol. Syst. (TRETS) 8(2), 1–22 (2015). Special Section on FPL 2013
Letz, S., Zedler, M., Thierer, T., Schutz, M., Roth, J., Seiffert, R.: XML offload and acceleration with cell broadband engine. In: XTech: Building Web 2.0. XTech Conference (2006)
Moussalli, R., Halstead, R., Solloum, M., Najjar, W., Tsotras, V.: Efficient XML path filtering using GPUs. In: Proceedings of the 2nd International Workshop on Accelerating Data Management Systems (ADMS 2011) (2011)
Fischer, P., Teubner, J.: MXQuery with hardware acceleration. In: Proceedings of the IEEE 28th International Conference on Data Engineering (ICDE), pp. 1293–1296. IEEE (2012)
Koopman, P.: Stack Computers: The New Wave, 234 p. Ellis Horwood, Mountain View Press, Mountain View (1989)
Paysan, B.: b16-small—less is more. In: Proceedings of the EuroForth 2004, 9 July 2006
Bowman, J., Garage, W.: J1: a small Forth CPU core for FPGAs. In: Proceedings of the EuroForth 2010, pp. 1–4, January 2010
Kale, V.: Using the MicroBlaze processor to accelerate cost-sensitive embedded system development. Xilinx, WP469 (v1.0.1) (2016). https://www.xilinx.com/products/design-tools/microblaze.html#documentation. Accessed 11 Nov 2019
Sergiyenko, A., Molchanov, O., Orlova, M.: Nano-processor for the small tasks. In: 2019 IEEE 39th International Conference on Electronics and Nanotechnology (ELNANO), pp. 674–677. IEEE (2019)
Altmann, V., Skodzik, J., Danielis, P., Van N.P., Golatowski, F., Timmermann, D.: Real-time capable hardware-based parser for efficient XML interchange. In: Proceedings of the 9th International Symposium on Communication Systems, Networks & Digital Sign (CSNDSP), pp. 415–420 (2014)
Rani, A., Grover, N.: Novel design of 32-bit asynchronous (RISC) microprocessor & its implementation on FPGA. Int. J. Inf. Eng. Electron. Bus. (IJIEEB) 10(1), 39–47 (2018). https://doi.org/10.5815/ijieeb.2018.01.06
Daghooghi, T.: Design and development MIPS processor based on a high performance and low power architecture on FPGA. Int. J. Mod. Educ. Comput. Sci. (IJMECS) 5(5), 49–59 (2013). https://doi.org/10.5815/ijmecs.2013.05.06
Girard, O.: OpenMSP430. OpenCores, Rev. 1.13 (2013). http://opencores.org. Accessed 11 Nov 2019
Molchanov, O., Orlova, M., Sergiyenko, A.: Software/hardware co-design of the microprocessor for the serial port communications. In: Hu, Z., Petoukhov, S., Dychka, I., He, M. (eds.) Advances in Computer Science for Engineering and Education II, pp. 238–246. Springer, Cham (2020)
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Sergiyenko, A., Orlova, M., Molchanov, O. (2021). Hardware/Software Co-design for XML-Document Processing. In: Hu, Z., Petoukhov, S., Dychka, I., He, M. (eds) Advances in Computer Science for Engineering and Education III. ICCSEEA 2020. Advances in Intelligent Systems and Computing, vol 1247. Springer, Cham. https://doi.org/10.1007/978-3-030-55506-1_34
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