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DC Performance Analysis of Heterojunction Tunnel FET by Optimizing Various High-κ Materials: HfO2/ZrO2 with Low/High-κ Spacer

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Intelligent Techniques and Applications in Science and Technology (ICIMSAT 2019)

Part of the book series: Learning and Analytics in Intelligent Systems ((LAIS,volume 12))

Abstract

In this study, double gate tunnel field effect transistor with heterojunctions have been investigated by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Firstly, Different hetero high-κ dielectric materials like HfO2, ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. Secondly, high-κ/low-κ spacer is incorporated beside the channel-source and channel-drain region for better tunneling along the surface. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using Band-to-band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, achieves of ION (max.) as 1.52 × 10−5 A/µm. further with low-κ spacer engineering, the subthreshold swing (ss) has also been recorded best as 19.76 mV/decade in comparison with conventional HTFET structures, can serve as better alternative tunnel FETs in low power logic applications.

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References

  1. Seabaugh, C., Zhang, Q.: Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 98(12), 2095–2110 (2010)

    Article  Google Scholar 

  2. Choi, W.Y., Park Lee, B.G., Liu, K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)

    Article  Google Scholar 

  3. Choi, W.Y., Lee, W.: Hetero-gate-dielectric tunneling fieldeffect transistors. IEEE Trans. Electron Devices 57(9), 2317–2319 (2010)

    Article  Google Scholar 

  4. Jagadesh Kumar, M., Ramaswamy, S.: Double gate symmetric tunnel FET: investigation and analysis. IET Circuits Devices Syst. 11(4), 365–370 (2017)

    Article  Google Scholar 

  5. Wisniewski, P., Majkusiak, B.: Modeling the tunnel field-effect transistor based on different tunneling path approaches. IEEE Trans. Electron Devices 65(6), 2626–2631 (2018)

    Article  Google Scholar 

  6. Sandow, C., et al.: Impact of electrostatics and doping concentrations on the performance of silicon tunnel field –effect transistors. Solid-State Electron. 53, 1126–1129 (2009)

    Article  Google Scholar 

  7. Chien, N.D., Shih, C.-H.: Oxide thickness- dependent effects of source doping profile on the performance of single and double tunnel field- effect transistors. Superlattices Microstruct. 102, 284–299 (2017)

    Article  Google Scholar 

  8. Pon, A., Carmel, S., Bhattacharyya, A., Ramesh, R.: Performance analysis of asymmetric dielectric modulated dual short gate tunnel field effect transistor. Superlattices Microstruct. 113, 608–615 (2018)

    Article  Google Scholar 

  9. Jhaveri, R., Nagavarapu, V., Woo, J.: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58(1), 80–86 (2011)

    Article  Google Scholar 

  10. Koester, S.J., Lauer, I., Majumdar, A., Cai, J., Sleight, J., Bedell, S., Solomon, P., Laux, S., Chang, L., Koswatta, S., Haensch, W., Tomasini, P., Thomas, S.: Are Si/SiGe tunneling field-effect transistors a goodidea? ECS Trans. 33(6), 357–361 (2010)

    Article  Google Scholar 

  11. Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-k gatedielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)

    Article  Google Scholar 

  12. Charles Pravin, J., Nirmal, D., Prajoon, P., Ajayan, J.: Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications. Physica E Low-dimension. Syst. Nanostruct. 83, 95–100 (2016)

    Article  Google Scholar 

  13. Kao, K.-H., Verhulst, A.S., Vandenberghe, W.G.: Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59(2), 292–301 (2012)

    Article  Google Scholar 

  14. Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.C.: Doublegate strained-Geheterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope. In: IEDM Technical Digest, pp. 947–949 (2008)

    Google Scholar 

  15. Nayfeh, O.M., Chleirigh, C.N., Hennessy, J., Gomez, L., Hoyt, J.L., Antoniadis, D.A.: Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions. IEEE Electron Device Lett. 29(9), 1074–1077 (2008)

    Article  Google Scholar 

  16. Kim, S.H., Kam, H., Hu, C., Liu, T.K.: Germanium-source tunnel field effect transistors with record high ION/IOFF. In: VLSI Symposium Technical Digest, pp. 178–179 (2009)

    Google Scholar 

  17. Upasana, Narang, R., Saxena, M., Gupta, M.: Modeling and TCAD assessment for gate material and gate dielectric engineered TFET architectures: circuit-level investigation for digital applications. IEEE Trans. Electron Devices 62(10), 3348–3356 (2015)

    Article  Google Scholar 

  18. Knoch, J., Appenzeller, J.: Modeling of high-performance p-type III–V heterojunction tunnel FETs. IEEE Electron Device Lett. 3(4), 305–307 (2010)

    Article  Google Scholar 

  19. Verhulst, S., Vandenberghe, W.G., Maex, K., De Gendt, S., Heyns, M., Groeseneken, G.: Complementary silicon-based heterostructure tunnel-FETs with high tunnelrates. IEEE Electron Device Lett. 29(12), 1398–1401 (2008)

    Article  Google Scholar 

  20. Nigam, K., Kondekar, P., Sharma, D.: Approach for ambipolar behaviour suppression in tunnel FET by workfunction engineering. Micro Nano Lett. 11(8), 460–464 (2016)

    Article  Google Scholar 

  21. Gracia, D., Nirmal, D., Nisha Justeena, A.: Investigation of Ge based double gate dual metal tunnel FET novel architecture using various hetero dielectric materials. Superlattices Microstruct. 109, 154–160 (2017)

    Article  Google Scholar 

  22. Dutta, R., Paitya, N.: TCAD performance analysis of P-I-N tunneling FETS under surrounded gate structure. SSRN-Elsevier (2019)

    Google Scholar 

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Correspondence to Ritam Dutta .

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Dutta, R., Guha, A., Rahaman, M., Paitya, N. (2020). DC Performance Analysis of Heterojunction Tunnel FET by Optimizing Various High-κ Materials: HfO2/ZrO2 with Low/High-κ Spacer. In: Dawn, S., Balas, V., Esposito, A., Gope, S. (eds) Intelligent Techniques and Applications in Science and Technology. ICIMSAT 2019. Learning and Analytics in Intelligent Systems, vol 12. Springer, Cham. https://doi.org/10.1007/978-3-030-42363-6_109

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