Abstract
The rapid deployment of embedded image processing applications have forced a paradigm shift from complete hardware and software based implementations providing best performance and lowest cost, respectively towards a hybrid approach, namely, application specific instruction-set processor (ASIP). In this paper, we evaluate the applicability of CuSP, a softcore DSP-ASIP, for image processing applications. CuSP has a Crimson DSP processor core and hardware accelerators directly coupled with the core offering improved performance with flexibility. Results show that CuSP offers performance improvement over standard softprocessor MicroBlaze by up to a factor of 36 times. Crimson DSP core alone gives up to 5.3 times lower execution cycles than MicroBlaze.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Atasu, K., Pozzi, L., Ienne, P.: Automatic application-specific instruction-set extensions under microarchitectural constraints. In: Proceedings of the 40th Annual Design Automation Conference, series DAC 2003, pp. 256–261. ACM, New York (2003)
Zhao, K., Bian, J., Dong, S.: A fast custom instructions identification algorithm based on basic convex pattern model for supporting ASIP automated design. In: 2007 11th International Conference on Computer Supported Cooperative Work in Design, pp. 121–126, April 2007
Samanta, S., Paik, S., Gangopadhyay, S., Chakrabarti, A.: Processing of image data using FPGA-based microblaze core. In: Mantri, A., Nandi, S., Kumar, G., Kumar, S. (Eds.) HPAGC, series Communications in Computer and Information Science, vol. 169, pp. 241–246. Springer (2011)
McNichols, J.M., Balster, E.J., Turri, W.F., Hill, K.L.: Design and implementation of an embedded NIOS II system for JPEG2000 tier II encoding. Int. J. Reconfig. Comput. 2:2 (2013)
Hoozemans, J., Wong, S., Al-Ars, Z.: Using VLIW softcore processors for image processing applications. In: 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 315–318, July 2015
Shrimal, D., Kumar Jain, M.: Instruction customization: a challenge in ASIP realization. Int. J. Comput. Appl. 98(15), 22–26 (2014)
Liu, D.: Embedded DSP Processor Design, vol. 2. Elsevier (2008)
Vityazev, S., Kharin, A., Savostyanov, V., Vityazev, V.: TMS320C66x multicore DSP efficiency in radar imaging applications. In: 2015 4th Mediterranean Conference on Embedded Computing (MECO), pp. 115–118, June 2015
Rangarajan, P., Kutraleeshwaran, V., Vaasanthy, K., Perinbam, R.P.: HDL synthesis and simulation of eight bit DSP based micro-controller for image processing applications. In: The 2002 45th Midwest Symposium on Circuits and Systems MWSCAS-2002, vol. 3, pp. III–609–612, August 2002
Liu, D., Tell, E.: Senior Instruction Set Manual. Linkoping University, Tech. Rep. (2008)
Tell, E., Olausson, M., Liu, D.: A general DSP processor at the cost of 23K gates and 1/2 a man-year design time. In: 2003 IEEE International Conference on Acoustics, Speech and Signal Processing, Proceedings ICASSP 2003, vol. 2, pp. II–657–660, April 2003
Lilja, D., Sapatnekar, S.: Designing Digital Computer Systems with Verilog. Cambridge University Press, Cambridge (2004)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this paper
Cite this paper
Sohail, S., Saeed, A., Rashid, H.u. (2019). Using DSP-ASIP for Image Processing Applications. In: Arai, K., Kapoor, S., Bhatia, R. (eds) Intelligent Computing. SAI 2018. Advances in Intelligent Systems and Computing, vol 858. Springer, Cham. https://doi.org/10.1007/978-3-030-01174-1_41
Download citation
DOI: https://doi.org/10.1007/978-3-030-01174-1_41
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-01173-4
Online ISBN: 978-3-030-01174-1
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)