Key words

1 Introduction

Selective excitation of genetically expressed proteins called “opsins,” capable of transforming a light signal into an electrical stimulus, is currently a powerful stimulation tool in neuroscience—called “optogenetics” [1, 2]. The light stimuli with variable intensity and temporal parameters are delivered usually through implanted multimode optic fibers coupled to LED or laser sources, while the evoked electrical activity might be detected by microelectrodes connected to low noise amplifiers. The microelectrodes are either twisted wires assembled into a miniaturized driving frame (i.e. microdrive) allowing depth positioning with accuracies in the micrometer range [3] or sometimes multielectrode arrays processed on silicon neuroprobes [4, 5]. Optogenetic neural perturbation and multichannel activity recordings can be performed either in open- or closed-loop. In a typical open-loop experiment, the stimulation parameters are set beforehand and the evoked responses are detected, while in closed-loop operation, the measured responses are used to determine the next stimulus parameters with the purpose of enhancing or suppressing the activity of particular cells or networks. Closed-loop operation has been used in studying the mechanisms of pathologically synchronized firing in a demand-controlled way [6–9], altering the functional connectivity and motor behavior through single-electrode stimulation based on extracellular recordings in the primate cortex [10] or in regulating the firing activity of the medial temporal lobe neurons through visual regulation in humans [11]. Closed-loop electrical stimulation that was triggered by a hippocampal place cell activation during sleep has been shown to induce behavioral changes [12]. Also, closed-loop optogenetic stimulation has been applied in seizure suppression [13, 14] or in modifying the functional interactions between neuronal populations in an in vitro model [15].

Closed-loop operation is advantageous when neural selectivity is desired, since it allows feedback-controlled stimulus optimization. The stimulus signal, in the case of optogenetics delivered through implanted optic fibers, can be triggered online whenever the neural activity is threshold detected [16, 17]. However, the online spike-sorting often has to be sacrificed in order to meet the speed requirements for real time decoding and/or visualization (millisecond latency) [11, 15]. Although several algorithms suitable for online signal processing have been reported [18–20], only few have actually been implemented in a real-time system [21].

We describe the implementation of a system allowing electrical recordings and optical stimulation , interfaced with a microdrive containing at least 24 tetrodes and at least two optical fibers. This system with 32 recording channels has been described in [22], but here we also show how the system can be scaled up to 96 channels at least. The prototype is closed-loop operated by implementing the template matching as a spike-sorting algorithm. Our CPU implementation is fast enough to process signals from 8 integrated tetrodes (32 channels) and deliver optical stimuli with a controlling frequency of 8 ms, while the GPU-based spike detection [23] offers enhanced data processing speed and is suitable for systems containing up to 128 channels.

Such closed-loop opto-electronic systems are valuable tools in studying dynamic brain processes in neuroscience.

2 System Configuration and Assembly

The hardware configuration shown in Fig. 1 allows data acquisition from 96 parallel channels together with reliable and fast signal processing capability and controlled delivery of light pulses with selectable temporal features.

Fig. 1
figure 1

Architecture of the 96-channel closed-loop platform

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A custom-designed microdrive loaded with 24 tetrodes (96 channels) allows accurate positioning of the tetrodes in the brain and in situ electrical activity detection. This microdrive allows also the positioning of three individually controllable multimode or single-mode optic fibers. The data acquisition system consists of three blocks: (1) three head-mounted amplifier boards, (2) a control unit, and (3) a processing unit (see Fig. 1). The assembly and operation of each component are described below.

2.1 Microdrive

A microdrive allowing the placement of up to 24 independently moveable tetrodes was designed for targeting forebrain brain areas such as the medial prefrontal cortex or the dorsal hippocampus. The drive shown in Fig. 2 (adapted from a design described [24]) consists of a 3D printed plastic shell, with 24 screw-driven shuttles allowing adjustment of each tetrode depth.

Fig. 2
figure 2

Microdrive for 24 recording tetrodes and up to three optic fibers: (a) Electrode interface board (EIB) scheme with (a) Omnetics connector, (b) ground connection, (c) fiber microdrive screw hole, (d) tetrode pin, (e) attachment screw hole; (b) photograph of the microdrive with the tetrode-fiber array: (a) fiber connector sleeve, (b) Omnetics connector, (c) fiber microdrive, (d) EIB, (e) tetrode-fiber array, (f) fiber, (g) tetrode microdrive, (h) tetrode; (c) cross-sectional view through the tetrode bundle with highlighted tetrode (red dots) and fiber (blue dots) positions; dashed white circles highlight the ring arrangement of the tetrodes around the fibers

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Tetrodes are made out of four twisted strands of Teflon-insulated 13 μm diameter Nichrome (Sandvik, Halstahammar, Sweden) wire. The insulation is melt after twisting, so that the four strands stick to one another. Tetrodes are then successively inserted in polyimide tubes (inner diameter: 0.0071″, outer diameter: 0.0116″, High Performance Conductors, Inc., Inman, SC) that are further glued to the shuttles.

The microdrive can contact the brain by mean of an exit bundle, where the guide tubes that protect each tetrode can be arranged in one or more groups, targeting different brain areas.

After the drive assembly, the tetrode tips were freshly cut and gold electroplated to a final impedance of 300–500 kΩ, using a Nano-Z computer-controlled current source (Neuralynx, Bozeman, MT).

2.2 Electrode Interface Board (EIB)

A custom PCB designed and commercialized by Atlas Neuroengineering—http://www.atlasneuro.com/—ensures the tetrode connection to the amplifier headstage and the vertical, central positioning of the optic fibers. By using a similar driving system, as for tetrodes, the optic fibers can be individually moved up and down in small increments and with high precision. Three 44 pin tetrode connectors (nanoseries), provided by Omnetics Connector Corporation—http://www.omnetics.com—are triangularly arranged around the central hole allowing the insertion of the fibers. A more cost-effective alternative for the Omnetics connectors is provided by the SlimStack™ connectors from Molex—www.molex.com—although the Omnetics connectors, given their compatibility with commercial headstage (e.g. Neuralynx headstages), offer possibilities for additional validation using commercial data acquisition systems.

2.3 Controlled Light Delivery System

Both optic single mode (SM—core diameter size 5–10 μm) and multimode (MM—core diameter size 100–200 μm) fibers can be implanted in the brain for light delivery depending on the desired stimulation volume. Numerical simulations based on the optical properties of rodent brain tissues have shown that fibers with higher numerical apertures (NA) and large core diameters generate larger and more uniform irradiance distribution volumes in the brain. On the other hand, for highly localized stimulation of particular cell groups, SM fibers might be more suitable.

Depending on the used fiber and desired power levels, light sources for optogenetics experiments include lasers, LEDs, and incandescent lamps. Some advantages and disadvantages of using different light sources in optogenetics have been discussed in [1]. Here, we point out that only coherent light can be coupled into SM fibers with sufficient efficiency. For the closed-loop system, one can use either DPSS lasers and as well as LEDs, respectively, for different experimental purposes. The DPSS lasers provide powerful and high coherent light beams, while the LEDs are simple and inexpensive. Both light sources can be electrically controlled to deliver pulses or continuous illumination over long periods.

The controlled illumination system (see Fig. 3) incorporates a DPSS laser (VM-TIM, DPSS-V473-150F) and an acousto-optic modulator (AOM) (AA-SA, MTS110-A3-VIS) to modulate the light intensity. AOMs, also called Bragg cells, use the acousto-optic effect to diffract and shift the frequency of light using sound waves (usually at radio-frequency). When one of the high-order outputs is coupled into the optical fiber, the emitted light power at the other fiber end changes linearly to the amplitude of the radio-frequency signals applied on the AOM device. Therefore, by combining the AOM device and the DPSS laser, light patterns with changeable intensity, flexible duty cycle, and stable and accurate temporal resolution can be obtained. The maximum light intensity modulation can reach >100 kHz (sufficient for optogenetics experiments). In total, more than 25 % of the laser light can be coupled into a common SM fiber (10 μm core diameter) for optical communication. This efficiency increases to 60–70 % for a MM fiber with a core diameter larger than 50 μm.

Fig. 3
figure 3

Scheme of the controlled illumination system based on a DPSS laser and an AOM

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Light-emitting diodes (LEDs) are incoherent light sources, only suitable for MM fibers. The output power of LEDs depends on the electric current. A simple home-made, high-power LED driver can be used to support the pulse modulation in a cost-effective way. Additionally a commercial LED driver can be used (e.g. Thorlabs, DC2100).

2.4 Amplifier Boards for 96 Channels Data Acquisition

Three head-mounted boards (i.e. headstages), each of 32 channels sharing the same architecture (see Fig. 4), interface with the tetrode-containing microdrive through a Slimstack Molex/Omnetic connectors, and are connected with the control unit via a custom cable. Each board includes an Intan amplifier (32 channels) and an ADC. Each headstage communicates to the control unit through seven digital signal lines, which are: (1) the digital input channel selector, commanding the amplifier to sample the next channel when this line is activated; (2) digital channel reset, which commands the amplifier to return to the first input channel; (3) digital settle, for rapidly discharging all capacitors in the front end amplifiers to ground in the event of the amplifier saturation; (4) ADC signal conversion, which initiates the conversion and outputs the most significant bits on the falling edge when the conversion is complete; (5) ADC clock signal, which outputs the remaining data bits at subsequent falling edges at the acquisition phase; (6) serial digital output of the ADC, returning the converted acquired signal; and (7) the return ADC clock signal, which ensures accurate signal acquisition at the computer’s side.

Fig. 4
figure 4

(a) Photographs of one headstage (top and bottom views) (PCB size: 29.5 mm × 43.4 mm), containing a miniature connector, a packaged amplifier, an ADC, and digital isolators; (b) schematic illustrations of the signal paths. Pre-amplification = 100×, amplification = 2×, filter bandwidth = 0.2–5000 Hz, multiplexing ratio = 32:1, 16-bit ADC and digital isolators

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The 32-channel amplifier is the RHA2132 chip (Intan technologies html). Neural signals are recorded against a common reference electrode. The ground is connected to the drive ground. Although the amplifier gain is fixed at 200×, the signal bandwidth can be set by external resistors between 0.2 and 5 kHz. The amplifier is dc-coupled, with a gain of 1 at 0 Hz. The multiplexed signals are digitized with 16-bit resolution (AD7980) before sending them to the digital I/O board.

The integrated multiplexers permit sampling speeds of up to 31.25 kSps (kilosamples per second) per channel. When a DAQ device (NI, PCI-6259) with a maximum aggregate sampling rate of 10 MHz is used for the 32-channel system, the sampling rate can reach up to 400 kSps (=1/2500 ns) or 12.5 kSps per channel. The reduced value results from the TTL minimum pulse width generated by the DAQ card clock of 100 ns (=1/10 MHz). Considering the requirements of the ADC conversion and acquisition time, we choose to set a fixed cycle time of 2500 ns (i.e. 900 ns of conversion and 16 × 100 ns of acquisition of 16-bit data samples), The high digital transmission speed of 10 MHz can cause several side effects, such as ringing, crosstalk, reflections, and ground bounce. To ensure the signal integrity, impedance bridging source termination and line drivers are implemented.

For the 96-channel system, the data acquisition is developed from a multifunction reconfigurable I/O board (NI, PCIe-7842R) armed with a programmable field-programmable gate array (FPGA) chip. The cycle time can thus be further reduced to 1540 ns (i.e. 900 ns of conversion and 16 × 40 ns of acquisition of 16-bit data samples), resulting in the sampling rate of 649 or 20.3 kSps per channel. Tests with shorter clock periods (<40 ns) show distortion in the TTL pulse. Data acquisition on 96 channels is achieved when the three head-stages perform in parallel on the FPGA device. The extension potential of the acquisition channels depends on the hardware resources in the system.

The amplifier board operates with two battery-supplied power sources: a regulated +3 V and a +5 V source, respectively. A 2.5 V reference voltage (ADP1710) is used for the ADC conversion. The digital isolators (ADUM1400 series) are used to decouple the ground of the amplifier board from the noisy computer ground and eliminate ground loops. These digital isolators are included in a home-made signal collection board (SCB), which is connected to the FPGA card (National Instrument, PCIe-7842R) via a commercial high-performance shielded cable (National Instrument, SHC68-68-RMIO). The signal lines from three headstages meet at this SCB before communicating to the control unit. Since, for animal experimenting purposes, the cables between the headstages and the SCB must be flexible and robust, light weight, and with low cross-talk at high frequencies, we customized cables that contain 8 pairs of twisted insulated wires. The diameter of the wires is 130 μm, and the total diameter of the cable is ~1.5 mm. These cables have been tested to work at frequencies up to 40 MHz with a length of 3 m.

3 Software

Custom software controlling the acquisition visualization and signal analysis consists of two parts: (1) the hardware-timed acquisition and (2) the online signal processing.

3.1 Hardware-Timed Acquisition

The real-time data acquisition is timed by the FPGA clock (an embedded FPGA chip for the DAQ device PCI-6259). The software is developed on a Windows 7 64-bit platform running Labview 2012. Within the Labview environment, programming and accessing the FPGA occurs at two sides, device and host. The device side, programmed within the Labview FPGA module, serves for the TTL pulse generation and data buffering, interfacing the PCB boards and the host computer. FIFO memory buffers were designed to balance the hardware acquisition and reading the values by the host program. The programming codes are multiplicated to interface the three headstages in parallel. Real-time digital signal filtering can also be optionally implemented in the FPGA. Finally, the programming codes for the device side are compiled and written to the FPGA chip as a bit file. At the host side, the programs mainly include three functions in parallel loops: (1) to invoke the device program and read the values from the FIFO buffer, (2) perform the signal processing, and (3) store the data. The synchronization among these three functions depends on the processing and storing speeds. For example, some signals might have to be skipped when the spike-sorting program takes more time than the data acquisition. Therefore, for a large number of recording channels (e.g. 96 channels) we implemented the spike-sorting on a GPU platform.

3.2 Online Signal Processing Based on the GPU

The signal-processing algorithm consists of filtering, spike detection, and classification steps. The GPU implementation is schematically illustrated in Fig. 5. The data read from the FIFO memory buffer are firstly transferred from the host computer memory to the GPU memory and converted into 32-bit floating-point type (single precision). If the signals have not been processed by a filter operator (e.g. a simpler finite impulse response filter) on the FPGA, a zero-phase bandpass filter is applied before the spike detection. Spikes can be detected by applying a negative amplitude threshold calculated based on the standard deviation of the background noise using the formula proposed by Quiroga et al. in [25]. Spike templates were extracted from a baseline-recording period at the beginning of the session. For the template definition, we have used a standard mixture-of-Gaussians expectation maximization (EM) algorithm [26]. Online spike-sorting is then performed using the simplest form of template matching, i.e. using the correlation between single spike waveforms and each template. The normalized correlation of the waveform with all templates is taken, and the spike assigned to the template resulting in the maximum correlation score. With the convolution theorem, a fast Fourier transformation algorithm was used to implement the correlation instead of the convolution in order to reduce the computation time. Finally, the results of the spike-sorting are sent back to the host memory. The system generates then the required stimulation strategy (depending on the experimental goals) immediately and sends a command to the light source. Figure 4 shows the architecture of the closed-loop system and the data flow.

Fig. 5
figure 5

Architecture of the closed-loop system with GPU spike-sorting

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Both programming and computation in this work can be implemented with a workstation hosting an NVIDIA GeForce GTX 680 GPU (PCIe 3.0 16× interface, 1536 cores at 1.006 GHz, 2.0 GB graphics memory), an Intel i7-3770 CPU (3.9 GHz) and a 16 GB host memory. In contrast to programming codes directly through NVIDIA’s Compute Unified Device Architecture (CUDA), one can employ the commercial software library, ArrayFire (Version 2.0, AccelerEyes, GA, USA) that makes GPU programming simpler by packaging most basic CUDA codes into array-based functions. This relatively simple scheme for GPU programming and GPU-memory access allows for faster and more flexible adaptation of the existing signal processing routines. Since we use Labview as a coding tool for data acquisition and system control, while the GPU-based spike-sorting codes are performed in VC++ (Visual Studio 2008, Professional Edition), we used a shared library compiled from VC++ scripts to implement the spike-sorting. Thus the VC++ scripts are first compiled to generate a dynamic link library (DLL) available for program platforms such as LabView.

4 Animal Surgeries

The protocol used by our team for the genetic targeting of a particular depolarizing opsin (i.e. ChR2) is described here. Other opsins or protocols may be selected depending of the experimental goals. Animal experiments should be always performed in accordance to the national and international regulations (in our case the national Belgian and European Union regulations and with the approval of the ethical committee of KU Leuven).

In a first surgical step, adeno-associated based viral vectors (AAV) , kindly provided by the laboratory of Prof. V. Baekelandt and the viral vector core facility of the KU Leuven, were stereotaxically injected to allow the expression of the opsin mChR2 based on the alphaCaMKII promoter in the target structures (medial prefrontal cortex: AP 3.5–4.5, ML 0.5, DV 1.8–3.5; dorsal hippocampus: AP −3.5, ML 2, DV 1.5–2.5), by means of a glass micro-pipette controlled by a micro-injector. The small craniotomies were then filled with a biocompatible silicon based elastomer, and the skin sutured.

At least 2 weeks are required for obtaining sufficient opsin expression levels. After this time, the microdrive implantation was performed on rats anesthetized with isoflurane (4 % induction, 1.5–2 % maintenance) that have also received subcutaneous carprofen for pain management. Craniotomies and dura dissection were performed above the target structure. The microdrive was then positioned and anchored to the skull by means of bone screws and dental cement. During recovery from surgery, the tetrodes were slowly advanced towards their target structure. Local field potential markers, such as hippocampal sharp waves, cortical delta waves, and spindles were used in order to guide the positioning process. After the tetrodes reached the desired location, electrophysiological recording were performed using the system described above, during quiet wakefulness or sleep. Various stimulation protocols can be applied according to both open- and closed-loop protocols, depending on the experimental goals.